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Paper Abstract and Keywords
Presentation 2013-03-05 10:50
High Level Resynthesis Approach of Reusable RTL Property
Msaato Tatsuoka, Mineo Kaneko (JAIST) VLD2012-145
Abstract (in Japanese) (See Japanese page) 
(in English) Similar to RTL language that has been used as a design entry for LSI, a high-level description language such as SystemC, C++, becomes one of the promising design entries in these days especially for large-size macro blocks. On the other hand, there are a large number of existing RTL properties, In most cases, they are reused as they are, and it is difficult to reuse those RTL properties with being optimized to a cutting-edge process technology. In this paper, we propose a resynthesis approach of reusable RTL properties, by which a superior macro block can be synthesized from an existing RTL property. Further, we have studied the technical issues and the effectiveness of our new approach.
Keyword (in Japanese) (See Japanese page) 
(in English) high level synthesis / conversion / SystemC / C/C++ / RTL / process technology / reuse / abstraction  
Reference Info. IEICE Tech. Rep., vol. 112, no. 451, VLD2012-145, pp. 55-60, March 2013.
Paper # VLD2012-145 
Date of Issue 2013-02-25 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-145

Conference Information
Committee VLD  
Conference Date 2013-03-04 - 2013-03-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2013-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) High Level Resynthesis Approach of Reusable RTL Property 
Sub Title (in English)  
Keyword(1) high level synthesis  
Keyword(2) conversion  
Keyword(3) SystemC  
Keyword(4) C/C++  
Keyword(5) RTL  
Keyword(6) process technology  
Keyword(7) reuse  
Keyword(8) abstraction  
1st Author's Name Msaato Tatsuoka  
1st Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
2nd Author's Name Mineo Kaneko  
2nd Author's Affiliation Japan Advanced Institute of Science and Technology (JAIST)
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Speaker Author-1 
Date Time 2013-03-05 10:50:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-145 
Volume (vol) vol.112 
Number (no) no.451 
Page pp.55-60 
#Pages 6 
Date of Issue 2013-02-25 (VLD) 

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