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Paper Abstract and Keywords
Presentation 2013-03-06 15:10
Trojan Circuit for Fault Analysis Countermeasure and its Implementation
Takaya Tsukadaira, Daisuke Matsushima (Meijo Univ.), Takeshi Kumaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.) VLD2012-161
Abstract (in Japanese) (See Japanese page) 
(in English) Recently, the threat of hardware Trojans in forged integrated circuits has become serious problem due to the advancement of reverse-engineering technologies. The hardware Trojan is a malicious hardware virus that is incorporated into the LSI circuit. When the hardware Trojan trigger is actuated, the LSI performs subversive operations, such as the leaking of important information. Almost all previous studies on a hardware Trojan focus on cryptographic circuits, because confidential information is generally protected using a cryptographic circuit. These previous studies adopted non-countermeasure circuits, although countermeasure circuits against illegal attacks are often used as cryptographic circuits in general. Therefore, this study proposes a new hardware Trojan for countermeasure circuits. Experimental results using FPGA show the threat of the proposed hardware Trojan.
Keyword (in Japanese) (See Japanese page) 
(in English) Fault Analysis / AES / Countermeasure Circuit / Hardware Trojan / / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 451, VLD2012-161, pp. 141-146, March 2013.
Paper # VLD2012-161 
Date of Issue 2013-02-25 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2012-161

Conference Information
Committee VLD  
Conference Date 2013-03-04 - 2013-03-06 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2013-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Trojan Circuit for Fault Analysis Countermeasure and its Implementation 
Sub Title (in English)  
Keyword(1) Fault Analysis  
Keyword(2) AES  
Keyword(3) Countermeasure Circuit  
Keyword(4) Hardware Trojan  
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Keyword(6)  
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Keyword(8)  
1st Author's Name Takaya Tsukadaira  
1st Author's Affiliation Meijo University (Meijo Univ.)
2nd Author's Name Daisuke Matsushima  
2nd Author's Affiliation Meijo University (Meijo Univ.)
3rd Author's Name Takeshi Kumaki  
3rd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
4th Author's Name Masaya Yoshikawa  
4th Author's Affiliation Meijo University (Meijo Univ.)
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Speaker Author-1 
Date Time 2013-03-06 15:10:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2012-161 
Volume (vol) vol.112 
Number (no) no.451 
Page pp.141-146 
#Pages 6 
Date of Issue 2013-02-25 (VLD) 

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