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Paper Abstract and Keywords
Presentation 2013-03-14 15:30
Multiplier with concurrent error detection by particial duplication
Kazushi Akimoto (Kyoto Univ.), Nobutaka Kito (Cyukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-99 DC2012-105
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a multiplier with concurrent error detection, which can detect the error more than the designated numerical value.The multiplier has two multipliers, original one and partial duplicated one for checking.These outputs are compared for error detection.The partial duplicated multiplier calculates only most significant bits in product and has small area overhead.The proposed structure is suitable for floating point multiplication whose significand's msb is always one, because the proposed multiplier detects worse error.Thus, we show single precision floating point multiplication as an application, and evaluated it.
As a result, area overhead is 52\% of the original circuit when it compares only 16 bits on significand's 24 bits.This is half area overhead of duplication multiplier's one.
Keyword (in Japanese) (See Japanese page) 
(in English) concurrent error detection / soft error / particial duplication / multiplier / floating point multiplier / / /  
Reference Info. IEICE Tech. Rep., vol. 112, no. 482, DC2012-105, pp. 283-287, March 2013.
Paper # DC2012-105 
Date of Issue 2013-03-06 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2012-99 DC2012-105

Conference Information
Committee CPSY DC IPSJ-SLDM IPSJ-EMB  
Conference Date 2013-03-13 - 2013-03-14 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2013-03-CPSY-DC-SLDM-EMB 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Multiplier with concurrent error detection by particial duplication 
Sub Title (in English)  
Keyword(1) concurrent error detection  
Keyword(2) soft error  
Keyword(3) particial duplication  
Keyword(4) multiplier  
Keyword(5) floating point multiplier  
Keyword(6)  
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Keyword(8)  
1st Author's Name Kazushi Akimoto  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Nobutaka Kito  
2nd Author's Affiliation Cyukyo University (Cyukyo Univ.)
3rd Author's Name Naofumi Takagi  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2013-03-14 15:30:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # CPSY2012-99, DC2012-105 
Volume (vol) vol.112 
Number (no) no.481(CPSY), no.482(DC) 
Page pp.283-287 
#Pages 5 
Date of Issue 2013-03-06 (CPSY, DC) 

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