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Paper Abstract and Keywords
Presentation 2013-04-12 13:30
[Invited Talk] A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs
Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe (Toshiba) ICD2013-18
Abstract (in Japanese) (See Japanese page) 
(in English) A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / Sense Amplifier / Timing Generation / Random Variation / Statistic / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 1, ICD2013-18, pp. 91-96, April 2013.
Paper # ICD2013-18 
Date of Issue 2013-04-04 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2013-18

Conference Information
Committee ICD  
Conference Date 2013-04-11 - 2013-04-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Advanced Industrial Science and Technology (AIST) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2013-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) Sense Amplifier  
Keyword(3) Timing Generation  
Keyword(4) Random Variation  
Keyword(5) Statistic  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Atsushi Kawasumi  
1st Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
2nd Author's Name Yasuhisa Takeyama  
2nd Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
3rd Author's Name Osamu Hirabayashi  
3rd Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
4th Author's Name Keiichi Kushida  
4th Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
5th Author's Name Fumihiko Tachibana  
5th Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
6th Author's Name Yusuke Niki  
6th Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
7th Author's Name Sinichi Sasaki  
7th Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
8th Author's Name Tomoaki Yabe  
8th Author's Affiliation Toshiba Corporation Semiconductor & Strage Products Company (Toshiba)
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Speaker Author-1 
Date Time 2013-04-12 13:30:00 
Presentation Time 50 minutes 
Registration for ICD 
Paper # ICD2013-18 
Volume (vol) vol.113 
Number (no) no.1 
Page pp.91-96 
#Pages 6 
Date of Issue 2013-04-04 (ICD) 

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