Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2013-04-12 14:45
[Invited Lecture] A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges
Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki (STARC), Atsushi Kawasumi (Toshiba), Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. Tokyo) ICD2013-20
Abstract (in Japanese) (See Japanese page) 
(in English) 1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.
Keyword (in Japanese) (See Japanese page) 
(in English) SRAM / Hierarchical Bit Line / Non-Selected Column / Charge Share / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 1, ICD2013-20, pp. 103-108, April 2013.
Paper # ICD2013-20 
Date of Issue 2013-04-04 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2013-20

Conference Information
Committee ICD  
Conference Date 2013-04-11 - 2013-04-12 
Place (in Japanese) (See Japanese page) 
Place (in English) Advanced Industrial Science and Technology (AIST) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2013-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges 
Sub Title (in English)  
Keyword(1) SRAM  
Keyword(2) Hierarchical Bit Line  
Keyword(3) Non-Selected Column  
Keyword(4) Charge Share  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Shinichi Moriwaki  
1st Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
2nd Author's Name Yasue Yamamoto  
2nd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
3rd Author's Name Toshikazu Suzuki  
3rd Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
4th Author's Name Atsushi Kawasumi  
4th Author's Affiliation Toshiba Corporation (Toshiba)
5th Author's Name Shinji Miyano  
5th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
6th Author's Name Hirofumi Shinohara  
6th Author's Affiliation Semiconductor Technology Academic Research Center (STARC)
7th Author's Name Takayasu Sakurai  
7th Author's Affiliation The University of Tokyo (Univ. Tokyo)
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2013-04-12 14:45:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2013-20 
Volume (vol) vol.113 
Number (no) no.1 
Page pp.103-108 
#Pages 6 
Date of Issue 2013-04-04 (ICD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan