Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2013-05-16 14:35
A Linear Interpolation Unit Using Selector Logics
Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-6
Abstract (in Japanese) (See Japanese page) 
(in English) Interpolation is a technique that presumes a value between existing
data, which is often used for image scaling and correction of
distortion. A linear interpolation is one of the interpolation
techniques which interpolates inbetween values by linearly connecting
two known values. It is used practically in many cases because there
are comparatively small computation cost. In this paper, we propose a
high-speed linear interpolation circuit based on selector logics.
The proposed linear interpolation circuit reduces carry propagation
delay by using selector logics and then realizes a fast operation. We
have implemented our linear interpolation circuit in several ways and
evaluated each of them. We can find out that a selector-based linear
interpolation circuit where its partial products are summed up by
using the arithmetic operator reduces its delay by a maximum of 16%
compared with a linear interpolation circuit synthesized by using
arithmetic operators only.
Keyword (in Japanese) (See Japanese page) 
(in English) Selector Logics / Interpolation / Linear Interpolation / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 30, VLD2013-6, pp. 49-54, May 2013.
Paper # VLD2013-6 
Date of Issue 2013-05-09 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-6

Conference Information
Committee VLD IPSJ-SLDM  
Conference Date 2013-05-16 - 2013-05-16 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu International Conference Center 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System Design, etc. 
Paper Information
Registration To VLD 
Conference Code 2013-05-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Linear Interpolation Unit Using Selector Logics 
Sub Title (in English)  
Keyword(1) Selector Logics  
Keyword(2) Interpolation  
Keyword(3) Linear Interpolation  
Keyword(4)  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masashi Shio  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2013-05-16 14:35:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-6 
Volume (vol) vol.113 
Number (no) no.30 
Page pp.49-54 
#Pages 6 
Date of Issue 2013-05-09 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan