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Paper Abstract and Keywords
Presentation 2013-05-17 11:10
Evaluation of 3D on-chip network structures suitable to a data center
Takahide Ikeda, Yuichi Ohsita, Masayuki Murata (Osaka Univ) IN2013-20
Abstract (in Japanese) (See Japanese page) 
(in English) In a data center, servers cooperate with each other to handle a large amount of data. As the size of data increases, the energy consumption of the data center increases. To reduce the energy consumption of the data center, an architecture called on-chip data center has been proposed. In this architecture, a large number of CPUs are deployed on a single chip and connected by using Network on Chip (NoC). %However, the network structure suitable to the on-chip data center has not been discussed sufficiently.
In this paper, we focus on the 3-D network-on-chip, which reduce the energy consumption compared with 2-D network-on-chip. Then, we deploy packet switches and circuit switches, to accommodate the traffic between servers on the chip efficiently.
In this paper, we discuss the network structure by the following points; (1) connection between switches of different layers, (2) the layer of the switches connected to servers, and (3) the arrangement of switches on each layer.
We evaluate the energy consumption and the latency between servers. The result clarifies that to reduce the energy consumption and the latency, (1) switches on all layers should be connected to the switch on a certain layer, (2) all servers should connect to the switch on the same layer, and (3) all switches on each layer should be the same kind of switch.
Keyword (in Japanese) (See Japanese page) 
(in English) NoC / data center / power consumption / latency / 3D on-chip network / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 36, IN2013-20, pp. 49-54, May 2013.
Paper # IN2013-20 
Date of Issue 2013-05-09 (IN) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF IN2013-20

Conference Information
Committee RCS IN  
Conference Date 2013-05-16 - 2013-05-17 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Wireless Internet, Multi-hop network, Mesh network, Network coding, Cross layer technique, Wireless communication, etc. 
Paper Information
Registration To IN 
Conference Code 2013-05-RCS-IN 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Evaluation of 3D on-chip network structures suitable to a data center 
Sub Title (in English)  
Keyword(1) NoC  
Keyword(2) data center  
Keyword(3) power consumption  
Keyword(4) latency  
Keyword(5) 3D on-chip network  
1st Author's Name Takahide Ikeda  
1st Author's Affiliation Osaka University (Osaka Univ)
2nd Author's Name Yuichi Ohsita  
2nd Author's Affiliation Osaka University (Osaka Univ)
3rd Author's Name Masayuki Murata  
3rd Author's Affiliation Osaka University (Osaka Univ)
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Speaker Author-1 
Date Time 2013-05-17 11:10:00 
Presentation Time 25 minutes 
Registration for IN 
Paper # IN2013-20 
Volume (vol) vol.113 
Number (no) no.36 
Page pp.49-54 
Date of Issue 2013-05-09 (IN) 

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