Paper Abstract and Keywords |
Presentation |
2013-06-21 16:00
An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core Kentaroh Katoh (TNCT) DC2013-14 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents an online Interconnect test of SoC with Boundary Scan Shift and embedded reconfigurable core. The proposed online test architecture consists of functional cores with boundary scan design and a relative small-sized embedded reconfigurable core. The extra area of the proposed online is smaller than conventional self-checking circuits or hardware redundancy approaches. Unlike conventional online BIST approach, the proposed online test does not hinder the functional operation. Therefore it is suitable to the chips for real-time applications. The experiments with ISCAS 89 benchmarks reveal that the error latency 4.3 (ms). The time-multiplexed test strategy reduces 24 % the area of the embedded reconfigurable core. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
SOC / online interconnect test / boundary scan / embedded reconfigurable core / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 104, DC2013-14, pp. 25-29, June 2013. |
Paper # |
DC2013-14 |
Date of Issue |
2013-06-14 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2013-14 |
Conference Information |
Committee |
DC |
Conference Date |
2013-06-21 - 2013-06-21 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design, Test, Verification |
Paper Information |
Registration To |
DC |
Conference Code |
2013-06-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core |
Sub Title (in English) |
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SOC |
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online interconnect test |
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boundary scan |
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embedded reconfigurable core |
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1st Author's Name |
Kentaroh Katoh |
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Tsuruoka National College of Technology (TNCT) |
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Speaker |
Author-1 |
Date Time |
2013-06-21 16:00:00 |
Presentation Time |
30 minutes |
Registration for |
DC |
Paper # |
DC2013-14 |
Volume (vol) |
vol.113 |
Number (no) |
no.104 |
Page |
pp.25-29 |
#Pages |
5 |
Date of Issue |
2013-06-14 (DC) |