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Paper Abstract and Keywords
Presentation 2013-07-22 09:50
Optimization Considering Dependence of Signal Propagation Time of SFQ Logic Gates on Bias Voltage
Mikio Otsubo, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2013-10
Abstract (in Japanese) (See Japanese page) 
(in English) Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz with low power consumption. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, increasing a critical current of Josephson junction and adding bias feeding line in the SFQ circuit control the dependence of the signal propagation time on bias voltage, that decreases a timing error and enables a wide operating margin at a high operating frequency. In this paper, we simulate the optimization of the logic circuits by controlling dependence of signal propagation time on bias voltage. The logic gates have been optimized taking the dependence of the propagation time on the bias voltage into account. Designed logic cells have larger controllability of their delay times without deterioration of the bias margins compared to the conventional logic cells.
Keyword (in Japanese) (See Japanese page) 
(in English) Single flux quantum circuits / Logic gates / Timing error / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 149, SCE2013-10, pp. 1-4, July 2013.
Paper # SCE2013-10 
Date of Issue 2013-07-15 (SCE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SCE2013-10

Conference Information
Committee SCE  
Conference Date 2013-07-22 - 2013-07-22 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikaishinkou-kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Signal processing technologies and their applications, etc. 
Paper Information
Registration To SCE 
Conference Code 2013-07-SCE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Optimization Considering Dependence of Signal Propagation Time of SFQ Logic Gates on Bias Voltage 
Sub Title (in English)  
Keyword(1) Single flux quantum circuits  
Keyword(2) Logic gates  
Keyword(3) Timing error  
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1st Author's Name Mikio Otsubo  
1st Author's Affiliation Yokohama National University (Yokohama National Univ.)
2nd Author's Name Yuki Yamanashi  
2nd Author's Affiliation Yokohama National University (Yokohama National Univ.)
3rd Author's Name Nobuyuki Yoshikawa  
3rd Author's Affiliation Yokohama National University (Yokohama National Univ.)
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Speaker Author-1 
Date Time 2013-07-22 09:50:00 
Presentation Time 25 minutes 
Registration for SCE 
Paper # SCE2013-10 
Volume (vol) vol.113 
Number (no) no.149 
Page pp.1-4 
#Pages 4 
Date of Issue 2013-07-15 (SCE) 

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