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Paper Abstract and Keywords
Presentation 2013-09-18 17:00
A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-24
Abstract (in Japanese) (See Japanese page) 
(in English) Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-efficient processors that map a target program's hot path to a reconfigurable datapath.
In this paper, we propose a Control-Flow Driven Data-Flow Switching (CDDS) variable datapath architecture for embedded applications that demand extremely low power consumption in a wide range of uses.
This architecture is characterized by following two features:
(1) achieving both flexibility and low energy consumption by limiting the scope of the dynamic reconfiguration,
(2) realizing smooth migration from the existing architecture by mapping the existing instruction sequence to the datapath.
Preliminary evaluation on small programs have revealed that the CDDS accelerator achieves approximately 3 to 6 times the performance/power improvements, compared to a base processor.
Keyword (in Japanese) (See Japanese page) 
(in English) Reconfigurable system / Processor architecture / Embedded system / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 221, RECONF2013-24, pp. 25-30, Sept. 2013.
Paper # RECONF2013-24 
Date of Issue 2013-09-11 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2013-24

Conference Information
Committee RECONF  
Conference Date 2013-09-18 - 2013-09-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Japan Advanced Institute of Science and Technology 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2013-09-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Restricted Dynamically Reconfigurable Architecture for Low Power Processors 
Sub Title (in English)  
Keyword(1) Reconfigurable system  
Keyword(2) Processor architecture  
Keyword(3) Embedded system  
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1st Author's Name Takeshi Hirao  
1st Author's Affiliation Hokkaido University (Hokkaido Univ.)
2nd Author's Name Dahoo Kim  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ.)
3rd Author's Name Itaru Hida  
3rd Author's Affiliation Hokkaido University (Hokkaido Univ.)
4th Author's Name Tetsuya Asai  
4th Author's Affiliation Hokkaido University (Hokkaido Univ.)
5th Author's Name Masato Motomura  
5th Author's Affiliation Hokkaido University (Hokkaido Univ.)
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Speaker Author-1 
Date Time 2013-09-18 17:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2013-24 
Volume (vol) vol.113 
Number (no) no.221 
Page pp.25-30 
#Pages 6 
Date of Issue 2013-09-11 (RECONF) 

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