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Paper Abstract and Keywords
Presentation 2013-10-07 10:55
Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2013-47 ICD2013-71 IE2013-47
Abstract (in Japanese) (See Japanese page) 
(in English) There are mainly two types of handshaking protocols in asynchronous circuit design; 2-phase handshaking protocol and 4-phase handshaking protocol. It may be difficult to implement the 2-phase handshaking circuits since they are based on the transition signaling, while they have no return-to-zero overhead. This paper proposes double-clock and dual-edge-triggered flip-flops for designing simple control circuits based on the two-phase handshaking protocol. They can directly deal with the two-phase handshaking signals, resulting in simple control circuits. The performance and the design constraints of the proposed flip-flops have been evaluated using the PTM 22nm HP device parameters.
Keyword (in Japanese) (See Japanese page) 
(in English) 2-phase handshake protocol / Double-clock FF / Dual-edge-triggered FF / Asynchronous circuits / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 235, VLD2013-47, pp. 7-12, Oct. 2013.
Paper # VLD2013-47 
Date of Issue 2013-09-30 (VLD, ICD, IE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-47 ICD2013-71 IE2013-47

Conference Information
Committee IE ICD VLD IPSJ-SLDM  
Conference Date 2013-10-07 - 2013-10-08 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2013-10-IE-ICD-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits 
Sub Title (in English)  
Keyword(1) 2-phase handshake protocol  
Keyword(2) Double-clock FF  
Keyword(3) Dual-edge-triggered FF  
Keyword(4) Asynchronous circuits  
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1st Author's Name Masashi Imai  
1st Author's Affiliation Hirosaki University (Hirosaki Univ.)
2nd Author's Name Tomohiro Yoneda  
2nd Author's Affiliation National Institute of Informatics (NII)
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Speaker Author-1 
Date Time 2013-10-07 10:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-47, ICD2013-71, IE2013-47 
Volume (vol) vol.113 
Number (no) no.235(VLD), no.236(ICD), no.237(IE) 
Page pp.7-12 
#Pages 6 
Date of Issue 2013-09-30 (VLD, ICD, IE) 

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