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Paper Abstract and Keywords
Presentation 2013-10-08 09:00
A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations
Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-54 ICD2013-78 IE2013-54
Abstract (in Japanese) (See Japanese page) 
(in English) As device feature size drops, interconnection delays often exceed gate delays.
We have to incorporate interconnection delays even in high-level synthesis.
Using RDR architectures is one of the effective solutions to this problem.
At the same time, process and delay variation also becomes a serious problem which may result in several timing errors.
How to deal with this problem is another key issue in high-level synthesis.
Thus, we have proposed a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures.
In this paper, we evaluate our high-level synthesis algorithm comparing several existing algorithms considering several situations.
Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
Keyword (in Japanese) (See Japanese page) 
(in English) Process and Delay Variation / Post-Silicon Tuning / High-Level Synthesis / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 235, VLD2013-54, pp. 41-46, Oct. 2013.
Paper # VLD2013-54 
Date of Issue 2013-09-30 (VLD, ICD, IE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-54 ICD2013-78 IE2013-54

Conference Information
Committee IE ICD VLD IPSJ-SLDM  
Conference Date 2013-10-07 - 2013-10-08 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To VLD 
Conference Code 2013-10-IE-ICD-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations 
Sub Title (in English)  
Keyword(1) Process and Delay Variation  
Keyword(2) Post-Silicon Tuning  
Keyword(3) High-Level Synthesis  
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1st Author's Name Yuta Hagio  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Masao Yanagisawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Nozomu Togawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2013-10-08 09:00:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-54, ICD2013-78, IE2013-54 
Volume (vol) vol.113 
Number (no) no.235(VLD), no.236(ICD), no.237(IE) 
Page pp.41-46 
#Pages 6 
Date of Issue 2013-09-30 (VLD, ICD, IE) 

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