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Paper Abstract and Keywords
Presentation 2013-11-27 14:55
Suspicious timing error prediction using check points
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-67 DC2013-33
Abstract (in Japanese) (See Japanese page) 
(in English) Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error countermeasure techniques is increasing as well. Existing timing error detection/correction methods have difficulties in timing design since they have complex structure. Furthermore, their error correction is realized by re-run operation which results in low throughput. We have proposed a suspicious timing error prediction method (STEP method) which predicts timing error and corrects it with simple structure. STEP is based on checking timing errors by observing several checkpoints on signal paths. Since STEP is a timing error prediction method, we may have false positives and reduction of them is one of the largest problems. In this paper, we propose a method to reduce the false positives to optimize the checkpoints. The experimental results show that an operational frequency is increased by up to 2.4 times and its throughput is improved by up to 45%.
Keyword (in Japanese) (See Japanese page) 
(in English) timing error prediction / robust design / clock gating / / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 320, VLD2013-67, pp. 39-44, Nov. 2013.
Paper # VLD2013-67 
Date of Issue 2013-11-20 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-67 DC2013-33

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Suspicious timing error prediction using check points 
Sub Title (in English)  
Keyword(1) timing error prediction  
Keyword(2) robust design  
Keyword(3) clock gating  
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1st Author's Name Hiroaki Igarashi  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Youhua Shi  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Nozomu Togawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2013-11-27 14:55:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-67, DC2013-33 
Volume (vol) vol.113 
Number (no) no.320(VLD), no.321(DC) 
Page pp.39-44 
#Pages 6 
Date of Issue 2013-11-20 (VLD, DC) 

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