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Paper Abstract and Keywords
Presentation 2013-11-28 08:55
Mapping of Java bytecode to virtual CGRA with implementation in FPGA
Yuki Ogawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-47
Abstract (in Japanese) (See Japanese page) 
(in English) In embedded systems, the needs for rapid both low-cost development and high performance has been increasing recently.
The reuse of design assets is important technique in embedded systems.
However, in the specialized software for execution environment, the reusability is low generally.
We propose a technique in order to accelerate software with keeping its reusability.
The proposed technique accelerates the software processing speed by employing data path generation from the description style of software code.
It is implemented in FPGA after generating a virtual CGRA from software code.
In the verification results of using the electromagnetic wave propagation simulation, the execution time is faster by a factor of 960 than software execution by Nios II.
This result indicates the possibility that our proposed acceleration technique can realize both the reusability of Java software development assets and the increasing performance.
Keyword (in Japanese) (See Japanese page) 
(in English) Java / accelerator / embedded system / coarse grained reconfigurable arrays / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 325, RECONF2013-47, pp. 45-50, Nov. 2013.
Paper # RECONF2013-47 
Date of Issue 2013-11-20 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2013-47

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To RECONF 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Mapping of Java bytecode to virtual CGRA with implementation in FPGA 
Sub Title (in English)  
Keyword(1) Java  
Keyword(2) accelerator  
Keyword(3) embedded system  
Keyword(4) coarse grained reconfigurable arrays  
Keyword(5)  
Keyword(6)  
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1st Author's Name Yuki Ogawa  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Motoki Amagasaki  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Masahiro Iida  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Morihiro Kuga  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2013-11-28 08:55:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2013-47 
Volume (vol) vol.113 
Number (no) no.325 
Page pp.45-50 
#Pages 6 
Date of Issue 2013-11-20 (RECONF) 

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