Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2013-11-29 14:35
A Study on the Design of Processor System for Stream Processing
Yusuke Sekihara, Koji Yamazaki, Akihiko Miyazaki (NTT) VLD2013-101 DC2013-67
Abstract (in Japanese) (See Japanese page) 
(in English) Processing performance required for packet data transfer system has been improving year by year due to the high-speed data streaming. Dedicated LSI is used to transfer and analyze packets fast. However, since the manufacturing cost of the LSI has continued to rise by miniaturization of manufacturing process, that increasing the economic efficiency is more and more requested by extending the device lifetime and increase the flexibility of the system. In this paper, we propose a system for streaming data processing that can achieve the flexibility to various processes for the packet data. Devised system can reduce the latency of the memory access as compared to conventional general embedded-processor. We experimented the identification process of the packet data, and confirmed by implementing the FPGA that the proposed system can improve throughput by 26.5% with 10% increase of circuit area as compared to conventional general embedded-processor.
Keyword (in Japanese) (See Japanese page) 
(in English) RISC / Processor / Memory access / DPI / Bloom Filter / FPGA / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 320, VLD2013-101, pp. 287-292, Nov. 2013.
Paper # VLD2013-101 
Date of Issue 2013-11-20 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-101 DC2013-67

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study on the Design of Processor System for Stream Processing 
Sub Title (in English)  
Keyword(1) RISC  
Keyword(2) Processor  
Keyword(3) Memory access  
Keyword(4) DPI  
Keyword(5) Bloom Filter  
Keyword(6) FPGA  
Keyword(7)  
Keyword(8)  
1st Author's Name Yusuke Sekihara  
1st Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
2nd Author's Name Koji Yamazaki  
2nd Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
3rd Author's Name Akihiko Miyazaki  
3rd Author's Affiliation Nippon Telegraph and Telephone Corporation (NTT)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2013-11-29 14:35:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-101, DC2013-67 
Volume (vol) vol.113 
Number (no) no.320(VLD), no.321(DC) 
Page pp.287-292 
#Pages 6 
Date of Issue 2013-11-20 (VLD, DC) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan