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Paper Abstract and Keywords
Presentation 2013-11-29 13:45
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2013-99 DC2013-65
Abstract (in Japanese) (See Japanese page) 
(in English) Due to progressing the process technology in LSI, the yield of LSI chips is reduced by timing violations caused by delay variations. To recover the timing violations, programmable delay elements called PDEs are inserted into the clock tree before fabrication and their delays are tuned after fabrication. In this paper, we use PDEs with an ordered finite set of delay values and propose a delay tuning method of the PDEs for the yield improvement. Experimental results show that the proposed method is effective under Monte Carlo simulation.
Keyword (in Japanese) (See Japanese page) 
(in English) Delay variation / Timing violation / Yield / Programmable delay element / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 320, VLD2013-99, pp. 275-280, Nov. 2013.
Paper # VLD2013-99 
Date of Issue 2013-11-20 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-99 DC2013-65

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2013-11-27 - 2013-11-29 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2013 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2013-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement 
Sub Title (in English)  
Keyword(1) Delay variation  
Keyword(2) Timing violation  
Keyword(3) Yield  
Keyword(4) Programmable delay element  
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1st Author's Name Hayato Mashiko  
1st Author's Affiliation The University of Aizu (Univ. of Aizu)
2nd Author's Name Yukihide Kohira  
2nd Author's Affiliation The University of Aizu (Univ. of Aizu)
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Speaker Author-1 
Date Time 2013-11-29 13:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-99, DC2013-65 
Volume (vol) vol.113 
Number (no) no.320(VLD), no.321(DC) 
Page pp.275-280 
#Pages 6 
Date of Issue 2013-11-20 (VLD, DC) 

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