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Paper Abstract and Keywords
Presentation 2014-01-29 13:45
On Boolean Matching of LUT-based Circuits
Yusuke Matsunaga (Kyushu Univ.) VLD2013-127 CPSY2013-98 RECONF2013-81
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes two speed-up techniques for Boolean matching of
LUT-based circuits.
One is one-hot encoding technique for variables representing input
assignments. Though it requres more variables than existing binary
encoding technique, almost all added clauses using one-hot encoding are
binary clauses, which are suitable for efficient Boolean constraint
propagation.
The other is incremental search technique which shortens the evaluation
time for instances without successful matching.
Even for instances having matches, iterated executions of SAT solver
help to capture learnt clauses effective for later search.
So, its overhead is neglible.
Keyword (in Japanese) (See Japanese page) 
(in English) logic synthesis / technology mapping / FPGA / Boolean matching / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 416, VLD2013-127, pp. 149-154, Jan. 2014.
Paper # VLD2013-127 
Date of Issue 2014-01-21 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-127 CPSY2013-98 RECONF2013-81

Conference Information
Committee IPSJ-SLDM CPSY RECONF VLD  
Conference Date 2014-01-28 - 2014-01-29 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2014-01-SLDM-CPSY-RECONF-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On Boolean Matching of LUT-based Circuits 
Sub Title (in English)  
Keyword(1) logic synthesis  
Keyword(2) technology mapping  
Keyword(3) FPGA  
Keyword(4) Boolean matching  
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1st Author's Name Yusuke Matsunaga  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
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Speaker Author-1 
Date Time 2014-01-29 13:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-127, CPSY2013-98, RECONF2013-81 
Volume (vol) vol.113 
Number (no) no.416(VLD), no.417(CPSY), no.418(RECONF) 
Page pp.149-154 
#Pages 6 
Date of Issue 2014-01-21 (VLD, CPSY, RECONF) 

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