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| Presentation | 2014-02-10 09:50 A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT)  DC2013-81 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynchronous circuits can solove the problems of synchronous design. Synchronous-asynchronous converted techniques have been proposed as a method for implementing asynchronous circuits. This paper focuses on testing QDI asynchronous circuits converted from synchronous ones. Previous methods cannot detect faults to be irredundant by converted. We classified the faults to five types, and proposed DFT method in according to the each fault type. In the experimental results the proposed method achieved 100% fault coverage, and the area overhead of the proposed method is evaluated. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | asynchronous circuit / synchronous-asynchronous converted techniques / Quasi Delay Insensitive / design for testability / test generation / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 430, DC2013-81, pp. 13-18, Feb. 2014. | |
| Paper # | DC2013-81 | |
| Date of Issue | 2014-02-03 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2013-81 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2014-02-10 - 2014-02-10 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2014-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuit |
| Keyword(2) | synchronous-asynchronous converted techniques |
| Keyword(3) | Quasi Delay Insensitive |
| Keyword(4) | design for testability |
| Keyword(5) | test generation |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Sanae Mizutani |
| 1st Author's Affiliation | Nara National College of Technology (NNCT) |
| 2nd Author's Name | Hiroshi Iwata |
| 2nd Author's Affiliation | Nara National College of Technology (NNCT) |
| 3rd Author's Name | Ken'ichi Yamaguchi |
| 3rd Author's Affiliation | Nara National College of Technology (NNCT) |
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| Speaker | Author-1 |
| Date Time | 2014-02-10 09:50:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2013-81 |
| Volume (vol) | vol.113 |
| Number (no) | no.430 |
| Page | pp.13-18 |
| #Pages | 6 |
| Date of Issue | 2014-02-03 (DC) |
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