IEICE Technical Committee Submission System
Conference Paper's Information
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2014-02-10 16:40
An Implementation of Fault Tolerant Systems with Mutual Reconfiguration Based on Dual-FPGA Architecture
Takuma Mori, Shoichi Ohmoto, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2013-90
Abstract (in Japanese) (See Japanese page) 
(in English) This work presents a design of fault tolerant systems with mutual reconfiguration based on Dual-FPGA architecture.
The proposed design autonomously recovers from failure according to its cause by means of an adaptive recovery mechanism where two FPGAs cooperate together while monitoring and reconfiguring each other.
As a case study, such a fail-soft system, where a diffusion equation is solved numerically, is implemented on two FPGAs and evaluated in terms of area and performance.
Keyword (in Japanese) (See Japanese page) 
(in English) Mutual Reconfiguration / dual-FPGA architecture / fault tolerant / fail-soft / rollback / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 430, DC2013-90, pp. 67-72, Feb. 2014.
Paper # DC2013-90 
Date of Issue 2014-02-03 (DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF DC2013-90

Conference Information
Committee DC  
Conference Date 2014-02-10 - 2014-02-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) VLSI Design and Test, etc. 
Paper Information
Registration To DC 
Conference Code 2014-02-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Implementation of Fault Tolerant Systems with Mutual Reconfiguration Based on Dual-FPGA Architecture 
Sub Title (in English)  
Keyword(1) Mutual Reconfiguration  
Keyword(2) dual-FPGA architecture  
Keyword(3) fault tolerant  
Keyword(4) fail-soft  
Keyword(5) rollback  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Takuma Mori  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Shoichi Ohmoto  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Tsuyoshi Iwagaki  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Hideyuki Ichihara  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
5th Author's Name Tomoo Inoue  
5th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
Speaker Author-1 
Date Time 2014-02-10 16:40:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # DC2013-90 
Volume (vol) vol.113 
Number (no) no.430 
Page pp.67-72 
#Pages
Date of Issue 2014-02-03 (DC) 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan