Paper Abstract and Keywords |
Presentation |
2014-02-10 12:25
An Efficient Test Pattern Generator based on Mersenne Twister algorithm Sayaka Satonaka, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-86 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
To perform a high reliable manufacturing test with a reasonable cost, LFSR is widely used as test pattern generator. However, the LFSR-based pseudo random patterns are not suitable for sequential circuits.In this paper, we supposed that the Mersenne Twister is used as the test pattern generator instead of the LFSR to implement BIST into VLSIs. Mersenne Twister is one of pseudo random number generation algorithm and has the two advantages that are good randomness and huge period.Experimental results show that the test patterns generated through the Mersenne Twister are efficient with respect to the fault coverage and it is implemented with a comparable cost to the LFSR. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Manufacturing Test / BIST / Test Pattern Generator / Linear Feedback Shift Register / Mersenne Twister / / / |
Reference Info. |
IEICE Tech. Rep., vol. 113, no. 430, DC2013-86, pp. 43-48, Feb. 2014. |
Paper # |
DC2013-86 |
Date of Issue |
2014-02-03 (DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2013-86 |
Conference Information |
Committee |
DC |
Conference Date |
2014-02-10 - 2014-02-10 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kikai-Shinko-Kaikan Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
VLSI Design and Test, etc. |
Paper Information |
Registration To |
DC |
Conference Code |
2014-02-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An Efficient Test Pattern Generator based on Mersenne Twister algorithm |
Sub Title (in English) |
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Keyword(1) |
Manufacturing Test |
Keyword(2) |
BIST |
Keyword(3) |
Test Pattern Generator |
Keyword(4) |
Linear Feedback Shift Register |
Keyword(5) |
Mersenne Twister |
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1st Author's Name |
Sayaka Satonaka |
1st Author's Affiliation |
Nara National College of Technology (NNCT) |
2nd Author's Name |
Hiroshi Iwata |
2nd Author's Affiliation |
Nara National College of Technology (NNCT) |
3rd Author's Name |
Ken'ichi Yamaguchi |
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Nara National College of Technology (NNCT) |
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Speaker |
Author-1 |
Date Time |
2014-02-10 12:25:00 |
Presentation Time |
25 minutes |
Registration for |
DC |
Paper # |
DC2013-86 |
Volume (vol) |
vol.113 |
Number (no) |
no.430 |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2014-02-03 (DC) |
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