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Paper Abstract and Keywords
Presentation 2014-03-04 14:40
Self-Aligned Double and Quadruple Patterning-Aware Grid Routing
Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-151
Abstract (in Japanese) (See Japanese page) 
(in English) Self-Aligned Double and Quadruple Patterning (SADP, SAQP) are leading candidates for sub-$20~nm$ and sub-$14~nm$ node and beyond, but designing their feasible layouts must follow stricter constraints than in Litho-Etch-Litho-Etch process. Despite their robustness against overlay, SADP and SAQP are challenging processes since predicting wafer image instantly is almost impossible. We propose a new simple grid routing method for Spacer-Is-Dielectric (SID)-type SAQP process, preparing each node painted in different three colors interchangeably, so that we can design the target layout predicting the wafer image. The proposed grid structure utilizes conventional routing algorithms such as maze router etc. We can easily derive two kinds of mandrel patterns from the resultant data without complex coloring or decomposition methods.
Also, we propose SADP-aware routing method for Spacer-Is-Metal (SIM) process based on the same grid structure. For both SID-SAQP and SIM-SADP processes, classical maze-routing algorithm is implemented and the effectiveness is confirmed. To our best knowledge, this is the first SID-compliant SADP-aware routing method.
Keyword (in Japanese) (See Japanese page) 
(in English) Lithography / Self-Aligned Double Patterning / Self-Aligned Quadruple Patterning / Sidewall process / SADP / SAQP / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 454, VLD2013-151, pp. 99-104, March 2014.
Paper # VLD2013-151 
Date of Issue 2014-02-24 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD  
Conference Date 2014-03-03 - 2014-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2014-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Self-Aligned Double and Quadruple Patterning-Aware Grid Routing 
Sub Title (in English)  
Keyword(1) Lithography  
Keyword(2) Self-Aligned Double Patterning  
Keyword(3) Self-Aligned Quadruple Patterning  
Keyword(4) Sidewall process  
Keyword(5) SADP  
Keyword(6) SAQP  
Keyword(7)  
Keyword(8)  
1st Author's Name Chikaaki Kodama  
1st Author's Affiliation Toshiba Corporation (Toshiba)
2nd Author's Name Hirotaka Ichikawa  
2nd Author's Affiliation Toshiba Microelectronics Corporation (Toshiba Microelectronics)
3rd Author's Name Fumiharu Nakajima  
3rd Author's Affiliation Toshiba Corporation (Toshiba)
4th Author's Name Koichi Nakayama  
4th Author's Affiliation Toshiba Corporation (Toshiba)
5th Author's Name Shigeki Nojima  
5th Author's Affiliation Toshiba Corporation (Toshiba)
6th Author's Name Toshiya Kotani  
6th Author's Affiliation Toshiba Corporation (Toshiba)
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Speaker Author-1 
Date Time 2014-03-04 14:40:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-151 
Volume (vol) vol.113 
Number (no) no.454 
Page pp.99-104 
#Pages 6 
Date of Issue 2014-02-24 (VLD) 

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