Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2014-03-04 15:45
[Memorial Lecture] A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips
Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan Univ.), Tsung-Yi Ho (National Cheng-Kung Univ.) VLD2013-153
Abstract (in Japanese) (See Japanese page) 
(in English) Sample preparation, which is a front-end process to produce droplets of the desired target concentrations from input reagents, plays a pivotal role in every assay, laboratory, and application in biomedical engineering
and life science. The consumption of expensive sample is usually used to evaluate the effectiveness of a sample preparation process. In this paper, we present the fi rst optimal sample preparation algorithm based on a minimum-cost maximum-flow model. By using the proposed model, we can obtain the optimal cost of sample usage even for multiple-target concentrations. Experiments demonstrate that we can consistently achieve much better results not only in the consumption of sample usage but also the consumption of buffer usage as well as the waste amount when
compared with the state-of-the-art of the previous approaches.
Keyword (in Japanese) (See Japanese page) 
(in English) digital microfluidic biochips / sample preparation / minimum-cost maximum flow / integer equal flows / / / /  
Reference Info. IEICE Tech. Rep., vol. 113, no. 454, VLD2013-153, pp. 111-112, March 2014.
Paper # VLD2013-153 
Date of Issue 2014-02-24 (VLD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2013-153

Conference Information
Committee VLD  
Conference Date 2014-03-03 - 2014-03-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Okinawa Seinen Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Technology for System-on-Silicon 
Paper Information
Registration To VLD 
Conference Code 2014-03-VLD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips 
Sub Title (in English)  
Keyword(1) digital microfluidic biochips  
Keyword(2) sample preparation  
Keyword(3) minimum-cost maximum flow  
Keyword(4) integer equal flows  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Trung Anh Dinh  
1st Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
2nd Author's Name Shigeru Yamashita  
2nd Author's Affiliation Ritsumeikan University (Ritsumeikan Univ.)
3rd Author's Name Tsung-Yi Ho  
3rd Author's Affiliation National Cheng-Kung University (National Cheng-Kung Univ.)
4th Author's Name  
4th Author's Affiliation ()
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-2 
Date Time 2014-03-04 15:45:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2013-153 
Volume (vol) vol.113 
Number (no) no.454 
Page pp.111-112 
#Pages 2 
Date of Issue 2014-02-24 (VLD) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan