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| Paper Abstract and Keywords | ||
| Presentation | 2014-03-05 14:15 Post –Silicon Tuning of Body Biasing and Clock Skew for Low-Voltage LSI Tatsunori Kubo, Mineo Kaneko (JASIT)  VLD2013-163 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | As the device feature size decreases, operation speed increases and supply voltage decreases, variation of the signal propagation delay and the increase of the leakage current become serious problem. Post-silicon tuning techniques including skew tuning and body bias tuning are promissing solutions for these problems. In this paper , the combination of skew tuning and body bias tuning has been studied, and its potential for saving power consumption while keeping an operation speed of the circuit has been shown through simulations. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | clock slew / delay variation / threshold voltage / low power / low voltage / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 113, no. 454, VLD2013-163, pp. 159-163, March 2014. | |
| Paper # | VLD2013-163 | |
| Date of Issue | 2014-02-24 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2013-163 |
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| Conference Information | |
| Committee | VLD |
| Conference Date | 2014-03-03 - 2014-03-05 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Okinawa Seinen Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Technology for System-on-Silicon |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2014-03-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Post –Silicon Tuning of Body Biasing and Clock Skew for Low-Voltage LSI |
| Sub Title (in English) | |
| Keyword(1) | clock slew |
| Keyword(2) | delay variation |
| Keyword(3) | threshold voltage |
| Keyword(4) | low power |
| Keyword(5) | low voltage |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tatsunori Kubo |
| 1st Author's Affiliation | Japan Advanced Institute of Science and Technology (JASIT) |
| 2nd Author's Name | Mineo Kaneko |
| 2nd Author's Affiliation | Japan Advanced Institute of Science and Technology (JASIT) |
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| Speaker | Author-1 |
| Date Time | 2014-03-05 14:15:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2013-163 |
| Volume (vol) | vol.113 |
| Number (no) | no.454 |
| Page | pp.159-163 |
| #Pages | 5 |
| Date of Issue | 2014-02-24 (VLD) |
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