Paper Abstract and Keywords |
Presentation |
2014-04-18 15:15
[Invited Lecture]
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17 Link to ES Tech. Rep. Archives: ICD2014-17 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsec entry/exit delay penalty in power-on/power-off. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems due to its easy controllability for the power gating mode. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
power-gating / MPU / flip-flop / MTJ / nonvolatile / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 13, ICD2014-17, pp. 85-90, April 2014. |
Paper # |
ICD2014-17 |
Date of Issue |
2014-04-10 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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ICD2014-17 Link to ES Tech. Rep. Archives: ICD2014-17 |
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