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Paper Abstract and Keywords
Presentation 2014-04-18 15:15
[Invited Lecture] A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop
Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17
Abstract (in Japanese) (See Japanese page) 
(in English) We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsec entry/exit delay penalty in power-on/power-off. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems due to its easy controllability for the power gating mode.
Keyword (in Japanese) (See Japanese page) 
(in English) power-gating / MPU / flip-flop / MTJ / nonvolatile / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 13, ICD2014-17, pp. 85-90, April 2014.
Paper # ICD2014-17 
Date of Issue 2014-04-10 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ICD  
Conference Date 2014-04-17 - 2014-04-18 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Memory Device Technologies 
Paper Information
Registration To ICD 
Conference Code 2014-04-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop 
Sub Title (in English)  
Keyword(1) power-gating  
Keyword(2) MPU  
Keyword(3) flip-flop  
Keyword(4) MTJ  
Keyword(5) nonvolatile  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Hiroki Koike  
1st Author's Affiliation Tohoku University (Tohoku Univ.)
2nd Author's Name Noboru Sakimura  
2nd Author's Affiliation NEC Corporation (NEC)
3rd Author's Name Ryusuke Nebashi  
3rd Author's Affiliation NEC Corporation (NEC)
4th Author's Name Yukihide Tsuji  
4th Author's Affiliation NEC Corporation (NEC)
5th Author's Name Ayuka Morioka  
5th Author's Affiliation NEC Corporation (NEC)
6th Author's Name Sadahiko Miura  
6th Author's Affiliation NEC Corporation (NEC)
7th Author's Name Hiroaki Honjo  
7th Author's Affiliation NEC Corporation (NEC)
8th Author's Name Tadahiko Sugibayashi  
8th Author's Affiliation NEC Corporation (NEC)
9th Author's Name Takashi Ohsawa  
9th Author's Affiliation Tohoku University (Tohoku Univ.)
10th Author's Name Shoji Ikeda  
10th Author's Affiliation Tohoku University (Tohoku Univ.)
11th Author's Name Takahiro Hanyu  
11th Author's Affiliation Tohoku University (Tohoku Univ.)
12th Author's Name Hideo Ohno  
12th Author's Affiliation Tohoku University (Tohoku Univ.)
13th Author's Name Tetsuo Endoh  
13th Author's Affiliation Tohoku University (Tohoku Univ.)
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Speaker Author-1 
Date Time 2014-04-18 15:15:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2014-17 
Volume (vol) vol.114 
Number (no) no.13 
Page pp.85-90 
#Pages 6 
Date of Issue 2014-04-10 (ICD) 

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