Paper Abstract and Keywords |
Presentation |
2014-04-25 13:00
[Fellow Memorial Lecture]
Synchronous Circuit Design vs. Asynchronous Circuit Design
-- Trials to compare them from various aspects -- Tomohiro Yoneda (NII) CPSY2014-1 DC2014-1 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this talk, the asynchronous design, where execution is controlled in an event driven manner based on handshaking without using any global clock signals, is considered. Historically, this design style is old, and was applied in order to design and develop ILLIAC I in 1952 and ILLIAC II in 1962, which actually operated and were very powerful for its time. Later on, as everyone knows, the synchronous design, where operations are sequenced using global clocks, became widely accepted. However, as the clock frequency reaches several Gigahertz, serious problems such as the clock skew, power dissipation, and EMI (Electro-Magnetic Interference) problems due to the clock signal distribution arise, and thus, the asynchronous design that does not potentially suffer from those problems again attracts attention. Nevertheless, since most designers consider the asynchronous design difficult and the CAD support for it is very poor, it is far from the mainstream of the design style.
This talk tries to compare the synchronous design and the asynchronous design from various aspects. Firstly, after the historical facts for both design styles are briefly introduced, several technical issues for the asynchronous design are explained. Then, the timing constraints and delay models of both the styles are compared, and the power dissipation, potential performance, and so on are discussed qualitatively. Next, a router for the wormhole routing method is considered as a concrete example, and some important part of the router is actually designed using each design style, in order to analyze and compare both the design processes. Since I am an asynchronous-design person, it’s not easy to do a pretty fair comparison. Instead, this talk tries to figure out where the complication of the synchronous design comes from, from the asynchronous-design person’s point of view. Finally, some quantitative comparison of the two designs is tried. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Asynchronous design / Synchronous design / Event driven method / Wormhole routing / Router design / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 21, CPSY2014-1, pp. 1-1, April 2014. |
Paper # |
CPSY2014-1 |
Date of Issue |
2014-04-18 (CPSY, DC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2014-1 DC2014-1 |
Conference Information |
Committee |
CPSY DC |
Conference Date |
2014-04-25 - 2014-04-25 |
Place (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
CPSY |
Conference Code |
2014-04-CPSY-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Synchronous Circuit Design vs. Asynchronous Circuit Design |
Sub Title (in English) |
Trials to compare them from various aspects |
Keyword(1) |
Asynchronous design |
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Synchronous design |
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Event driven method |
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Wormhole routing |
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Router design |
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1st Author's Name |
Tomohiro Yoneda |
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National Institute of Informatics (NII) |
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Speaker |
Author-1 |
Date Time |
2014-04-25 13:00:00 |
Presentation Time |
50 minutes |
Registration for |
CPSY |
Paper # |
CPSY2014-1, DC2014-1 |
Volume (vol) |
vol.114 |
Number (no) |
no.21(CPSY), no.22(DC) |
Page |
p.1 |
#Pages |
1 |
Date of Issue |
2014-04-18 (CPSY, DC) |
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