Paper Abstract and Keywords |
Presentation |
2014-06-12 16:00
FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Set Associative Cache Kenji Kanazawa, Tsutomu Maruyama (Univ. of Tsukuba) RECONF2014-14 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
WalkSAT (WSAT) is one of the stochastic local search algorithms for Boolean Satisfiability (SAT) and Maximum Boolean Satisfiability (MaxSAT), and it is very suitable for hardware acceleration, because of its high
inherent parallelism. Formal verification is one of the most important applications of SAT and MaxSAT, however, the size of the formal verification problems is significantly larger than on-chip memory size, and most of the data have to be placed in off-chip DRAM. In this approach, however, the acceleration was still limited by the DRAM access delay. In this paper, we propose a method to hide the access delay by using on-chip memory banks as a variable-way associative cache memory. With this cache memory, up to 60% DRAM access delay can be hidden, and the performance can be improved up to 26%. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / SAT / MaxSAT / WSAT / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 75, RECONF2014-14, pp. 73-78, June 2014. |
Paper # |
RECONF2014-14 |
Date of Issue |
2014-06-04 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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RECONF2014-14 |
Conference Information |
Committee |
RECONF |
Conference Date |
2014-06-11 - 2014-06-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Katahira Sakura Hall |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Reconfigurable Systems, etc. |
Paper Information |
Registration To |
RECONF |
Conference Code |
2014-06-RECONF |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Set Associative Cache |
Sub Title (in English) |
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FPGA |
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SAT |
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MaxSAT |
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WSAT |
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1st Author's Name |
Kenji Kanazawa |
1st Author's Affiliation |
University of Tsukuba (Univ. of Tsukuba) |
2nd Author's Name |
Tsutomu Maruyama |
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University of Tsukuba (Univ. of Tsukuba) |
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Speaker |
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Date Time |
2014-06-12 16:00:00 |
Presentation Time |
25 minutes |
Registration for |
RECONF |
Paper # |
RECONF2014-14 |
Volume (vol) |
vol.114 |
Number (no) |
no.75 |
Page |
pp.73-78 |
#Pages |
6 |
Date of Issue |
2014-06-04 (RECONF) |
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