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Paper Abstract and Keywords
Presentation 2014-06-19 09:30
Process Design of High-k/Ge Gate Stack for Improving Thermal Stability and Interface Properties in Sub-1-nm Regime
Ryohei Asahara, Takuji Hosoi, Takayoshi Shimura, Heiji Watanabe (Osaka Univ.) SDM2014-43
Abstract (in Japanese) (See Japanese page) 
(in English) Suppression of GeOx formation and Ge diffusion into high-k layer is important to develop sub-1-nm EOT metal/high-k gate stacks for advanced Ge MOSFETs. In this work, high-k/Ge gate stack with an ultrathin EOT was fabricated by controlling interface reaction using ultrathin AlOx interlayer and plasma oxidation through the high-k layer. We also investigated HfOx formation process, plasma oxidation condition and metal electrode thickness to improve thermal stability and interface properties. An EOT of 0.85 nm with significantly reduced Dit and thermal stability up to 500C was successfully obtained for Pt/HfO2/AlOx/GeOx/Ge gate stack.
Keyword (in Japanese) (See Japanese page) 
(in English) Germanium (Ge) / high-permittivity (high-k) gate dielectrics / hafnium oxide（HfO2） / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 88, SDM2014-43, pp. 1-5, June 2014.
Paper # SDM2014-43 
Date of Issue 2014-06-12 (SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SDM  
Conference Date 2014-06-19 - 2014-06-19 
Place (in Japanese) (See Japanese page) 
Place (in English) VBL, Nagoya Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Material Science and Process Technology for MOS Devices and Memories 
Paper Information
Registration To SDM 
Conference Code 2014-06-SDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Process Design of High-k/Ge Gate Stack for Improving Thermal Stability and Interface Properties in Sub-1-nm Regime 
Sub Title (in English)  
Keyword(1) Germanium (Ge)  
Keyword(2) high-permittivity (high-k) gate dielectrics  
Keyword(3) hafnium oxide（HfO2）  
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1st Author's Name Ryohei Asahara  
1st Author's Affiliation Osaka University (Osaka Univ.)
2nd Author's Name Takuji Hosoi  
2nd Author's Affiliation Osaka University (Osaka Univ.)
3rd Author's Name Takayoshi Shimura  
3rd Author's Affiliation Osaka University (Osaka Univ.)
4th Author's Name Heiji Watanabe  
4th Author's Affiliation Osaka University (Osaka Univ.)
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Speaker Author-1 
Date Time 2014-06-19 09:30:00 
Presentation Time 20 minutes 
Registration for SDM 
Paper # SDM2014-43 
Volume (vol) vol.114 
Number (no) no.88 
Page pp.1-5 
#Pages 5 
Date of Issue 2014-06-12 (SDM) 

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