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| Presentation | 2014-06-20 15:35 Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.)  DC2014-15 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We propose a floating-point multiplier with reduced precision error checking. The multiplier uses a truncated multiplier for checking of mantissa multiplication instead of a fully duplicated multiplier. The circuit area of the proposed multiplier is smaller than that of duplicated one. The truncated multiplier in the proposed multiplier is designed considering rounding in floating point operation, and the proposed multiplier can detect any errors larger than 1~ulp. We have evaluated circuit area of the proposed multiplier. Hardware overhead of a single-precision multiplier is about 70% and that of a double-precision one is about 80%. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | concurrent error checking / floating-point multiplier / duplication / truncated multiplier / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 99, DC2014-15, pp. 33-38, June 2014. | |
| Paper # | DC2014-15 | |
| Date of Issue | 2014-06-13 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2014-15 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2014-06-20 - 2014-06-20 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg. |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design/Test/Verification |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2014-06-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication |
| Sub Title (in English) | |
| Keyword(1) | concurrent error checking |
| Keyword(2) | floating-point multiplier |
| Keyword(3) | duplication |
| Keyword(4) | truncated multiplier |
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| 1st Author's Name | Nobutaka Kito |
| 1st Author's Affiliation | Chukyo University (Chukyo Univ.) |
| 2nd Author's Name | Kazushi Akimoto |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Naofumi Takagi |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-06-20 15:35:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2014-15 |
| Volume (vol) | vol.114 |
| Number (no) | no.99 |
| Page | pp.33-38 |
| #Pages | 6 |
| Date of Issue | 2014-06-13 (DC) |
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