Paper Abstract and Keywords |
Presentation |
2014-07-11 13:00
Accelerating Boolean Matching of LUT-based Circuits using CEGAR method Yusuke Matsunaga (Kyushu Univ.) CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper describes an accelerating technique for Boolean matching of LUT-based circuits, which is based on CEGAR (counter example guided abstraction refinement) method. CEGAR reduces the search space drastically both on SAT and UNSAT instances. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
logic synthesis / technology mapping / FPGA / Boolean matching / CEGAR / SAT / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 123, VLD2014-47, pp. 201-206, July 2014. |
Paper # |
VLD2014-47 |
Date of Issue |
2014-07-02 (CAS, VLD, SIP, MSS, SIS) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 |
Conference Information |
Committee |
CAS SIP MSS VLD SIS |
Conference Date |
2014-07-09 - 2014-07-11 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System, signal processing and related topics |
Paper Information |
Registration To |
VLD |
Conference Code |
2014-07-CAS-SIP-MSS-VLD-SIS |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Accelerating Boolean Matching of LUT-based Circuits using CEGAR method |
Sub Title (in English) |
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Keyword(1) |
logic synthesis |
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technology mapping |
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FPGA |
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Boolean matching |
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CEGAR |
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SAT |
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1st Author's Name |
Yusuke Matsunaga |
1st Author's Affiliation |
Kyushu University (Kyushu Univ.) |
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Speaker |
Author-1 |
Date Time |
2014-07-11 13:00:00 |
Presentation Time |
20 minutes |
Registration for |
VLD |
Paper # |
CAS2014-38, VLD2014-47, SIP2014-59, MSS2014-38, SIS2014-38 |
Volume (vol) |
vol.114 |
Number (no) |
no.122(CAS), no.123(VLD), no.124(SIP), no.125(MSS), no.126(SIS) |
Page |
pp.201-206 |
#Pages |
6 |
Date of Issue |
2014-07-02 (CAS, VLD, SIP, MSS, SIS) |
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