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Paper Abstract and Keywords
Presentation 2014-07-29 17:50
Development of Cipher implementation tool using GUI
Masashi Watanabe, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa (NDA) CPSY2014-31
Abstract (in Japanese) (See Japanese page) 
(in English) With the spread of heterogeneous computing, accelerators such as GPU are widely used. However, it
is not easy to write a software program that runs at high speed on accelerators. On the other hand, encryption
algorithms are evaluated with not only the strength but also the implementability and the performance. Therefore
it is important to compare the performance by throughput using accelerators. This paper proposes a development tool named SPT(Schematic to Program Translator) for high-speed processing of encryption as well as FPGA and many-core processor. In this tool, a C program is automatically generated from the gure drawn in accordance with the speci cations of the encryption algorithm. Moreover, many-core processor and FPGA can be easily used by passing the program to the C compiler, CUDA translator and high-level synthesis tool. As a result, codes generated by SPT can encrypt them accurately and show the performance that is equal to codes generated by person.
Keyword (in Japanese) (See Japanese page) 
(in English) GUI / Implementation of Encryption Circuit / AES / MISTY1 / Camellia / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 155, CPSY2014-31, pp. 125-129, July 2014.
Paper # CPSY2014-31 
Date of Issue 2014-07-21 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-31

Conference Information
Committee CPSY DC  
Conference Date 2014-07-28 - 2014-07-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Toki Messe, Niigata 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2014-07-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Development of Cipher implementation tool using GUI 
Sub Title (in English)  
Keyword(1) GUI  
Keyword(2) Implementation of Encryption Circuit  
Keyword(3) AES  
Keyword(4) MISTY1  
Keyword(5) Camellia  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Masashi Watanabe  
1st Author's Affiliation National Defense Academy of Japan (NDA)
2nd Author's Name Keisuke Iwai  
2nd Author's Affiliation National Defense Academy of Japan (NDA)
3rd Author's Name Hidema Tanaka  
3rd Author's Affiliation National Defense Academy of Japan (NDA)
4th Author's Name Takakazu Kurokawa  
4th Author's Affiliation National Defense Academy of Japan (NDA)
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Speaker Author-1 
Date Time 2014-07-29 17:50:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-31 
Volume (vol) vol.114 
Number (no) no.155 
Page pp.125-129 
#Pages 5 
Date of Issue 2014-07-21 (CPSY) 

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