Paper Abstract and Keywords |
Presentation |
2014-08-05 11:15
[Invited Talk]
Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Masato Oda, Shinobu Fujita, Shinichi Yasuda (Toshiba) SDM2014-75 ICD2014-44 Link to ES Tech. Rep. Archives: SDM2014-75 ICD2014-44 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CMOS logic is demonstrated. The MONOS transistors and low-voltage switching transistors are fabricated close to each other without deteriorating each performance. Furthermore, memory programming scheme is optimized to realize selective writing with no damage in the switching transistors. MONOS-based configuration memory has a half area of conventional SRAM, and it can be placed in each block in FPGA. That enables efficient power gating that offers low-power FPGA operation. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA / MONOS flash memory / Nonvolatile memory / Low power / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 114, no. 174, SDM2014-75, pp. 71-76, Aug. 2014. |
Paper # |
SDM2014-75 |
Date of Issue |
2014-07-28 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
SDM2014-75 ICD2014-44 Link to ES Tech. Rep. Archives: SDM2014-75 ICD2014-44 |
Conference Information |
Committee |
ICD SDM |
Conference Date |
2014-08-04 - 2014-08-05 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido Univ., Multimedia Education Bldg. |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
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Paper Information |
Registration To |
SDM |
Conference Code |
2014-08-ICD-SDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme |
Sub Title (in English) |
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Keyword(1) |
FPGA |
Keyword(2) |
MONOS flash memory |
Keyword(3) |
Nonvolatile memory |
Keyword(4) |
Low power |
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1st Author's Name |
Koichiro Zaitsu |
1st Author's Affiliation |
Toshiba Corporation (Toshiba) |
2nd Author's Name |
Kosuke Tatsumura |
2nd Author's Affiliation |
Toshiba Corporation (Toshiba) |
3rd Author's Name |
Mari Matsumoto |
3rd Author's Affiliation |
Toshiba Corporation (Toshiba) |
4th Author's Name |
Masato Oda |
4th Author's Affiliation |
Toshiba Corporation (Toshiba) |
5th Author's Name |
Shinobu Fujita |
5th Author's Affiliation |
Toshiba Corporation (Toshiba) |
6th Author's Name |
Shinichi Yasuda |
6th Author's Affiliation |
Toshiba Corporation (Toshiba) |
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Speaker |
Author-1 |
Date Time |
2014-08-05 11:15:00 |
Presentation Time |
50 minutes |
Registration for |
SDM |
Paper # |
SDM2014-75, ICD2014-44 |
Volume (vol) |
vol.114 |
Number (no) |
no.174(SDM), no.175(ICD) |
Page |
pp.71-76 |
#Pages |
6 |
Date of Issue |
2014-07-28 (SDM, ICD) |
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