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Paper Abstract and Keywords
Presentation 2014-09-05 15:35
GPU implementation of Ciphers using Schematic to Program Translator(SPT)
Masashi Watanabe, Keisuke Iwai, Hidema Tanaka, Takakazu Kurokawa (NDA) ISEC2014-52
Abstract (in Japanese) (See Japanese page) 
(in English) With the spread of heterogeneous computing, accelerators such as GPU are widely used. However, it is not easy to develop a software program that runs at high speed on accelerators. On the other hand, encryption algorithms are evaluated with not only the strength but also the implementability and the performance. Therefore it is important to compare the performance by throughput using accelerators. We proposed a development tool named SPT(Schematic to Program Translator) for high-speed processing of encryption as well as FPGA and many-core processor. In this paper, we discussed GPU implementation of Cipher using SPT. In this tool, a C program is automatically generated from the gure drawn in accordance with the speci cations of the encryption algorithm. Moreover, many-core processor, GPU and FPGA can be easily used by passing the program to the C compiler, CUDA translator and high-level synthesis tool. As a result, programs generated by CUDA transrator using C programs generated by SPT can perfprm encryption process correctly on GPU, however its performance
became slower than codes generated by person.
Keyword (in Japanese) (See Japanese page) 
(in English) GUI / Implementation of Encryption Circuit / AES / Camellia / CUDA / GPU / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 203, ISEC2014-52, pp. 35-42, Sept. 2014.
Paper # ISEC2014-52 
Date of Issue 2014-08-29 (ISEC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee ISEC  
Conference Date 2014-09-05 - 2014-09-05 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ISEC 
Conference Code 2014-09-ISEC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) GPU implementation of Ciphers using Schematic to Program Translator(SPT) 
Sub Title (in English)  
Keyword(1) GUI  
Keyword(2) Implementation of Encryption Circuit  
Keyword(3) AES  
Keyword(4) Camellia  
Keyword(5) CUDA  
Keyword(6) GPU  
Keyword(7)  
Keyword(8)  
1st Author's Name Masashi Watanabe  
1st Author's Affiliation National Defense Academy of Japan (NDA)
2nd Author's Name Keisuke Iwai  
2nd Author's Affiliation National Defense Academy of Japan (NDA)
3rd Author's Name Hidema Tanaka  
3rd Author's Affiliation National Defense Academy of Japan (NDA)
4th Author's Name Takakazu Kurokawa  
4th Author's Affiliation National Defense Academy of Japan (NDA)
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Speaker Author-1 
Date Time 2014-09-05 15:35:00 
Presentation Time 25 minutes 
Registration for ISEC 
Paper # ISEC2014-52 
Volume (vol) vol.114 
Number (no) no.203 
Page pp.35-42 
#Pages 8 
Date of Issue 2014-08-29 (ISEC) 

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