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Paper Abstract and Keywords
Presentation 2014-10-10 14:15
Study of Processor Core for Many-core Architecture Combining ALU Cascading and 3-way In-order Execution
Hajime Shimada (Nagoya Univ.), Ryotaro Kobayashi (Toyohashi Univ. of Tech.) CPSY2014-53
Abstract (in Japanese) (See Japanese page) 
(in English) Recent many-core processor frequently utilizes 2-way in-order execution core which is diverted from
high-performance embedded processor core due to good area / energy efficiency. However, current high-performance
embedded processor core aims to extend itself to 2-way out-of-order execution for performance. But it
requires additional circuit required for out-of-order execution so that it degrades area / energy efficiency. In this paper,
we discuss area / energy efficient processor core which is derived from in-order execution extension. Generally,
there’s almost no effectiveness in 3-way in-order execution because the effectiveness is limited by data dependency.
We consider to break this limitation by utilizing ALU cascading which executes several ALU arithmetic in one clock
cycle. ALU cascading cannot apply around upper bound of operatable clock frequency, but current processor infrequently
utilize upper bound of operatable clock frequency so that we thought there’s enough application chance. To
confirm effectiveness of the proposal, we compared processor performance among proposed 3-way in-order execution
with ALU cascading and 2-way out-of-order execution under SPEC CPU 2000 integer benchmarks. We confirmed
that the proposal gives better performance compared to 2-way out-of-order if the proposed core has 2 stage shorter
pipeline due to in-order execution.
Keyword (in Japanese) (See Japanese page) 
(in English) Processor architecture / Circuit area efficiency / Energy Efficiency / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 242, CPSY2014-53, pp. 37-42, Oct. 2014.
Paper # CPSY2014-53 
Date of Issue 2014-10-03 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY  
Conference Date 2014-10-10 - 2014-10-10 
Place (in Japanese) (See Japanese page) 
Place (in English) Meeting Room 303, International Conference Hall, Makuhari-Messe 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Computer Systems for User-centric Application 
Paper Information
Registration To CPSY 
Conference Code 2014-10-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study of Processor Core for Many-core Architecture Combining ALU Cascading and 3-way In-order Execution 
Sub Title (in English)  
Keyword(1) Processor architecture  
Keyword(2) Circuit area efficiency  
Keyword(3) Energy Efficiency  
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1st Author's Name Hajime Shimada  
1st Author's Affiliation Nagoya Univerisity (Nagoya Univ.)
2nd Author's Name Ryotaro Kobayashi  
2nd Author's Affiliation Toyohashi University of Technology (Toyohashi Univ. of Tech.)
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Speaker Author-1 
Date Time 2014-10-10 14:15:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-53 
Volume (vol) vol.114 
Number (no) no.242 
Page pp.37-42 
#Pages 6 
Date of Issue 2014-10-03 (CPSY) 

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