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Paper Abstract and Keywords
Presentation 2014-10-10 13:30
The power supply circuit simulation in consideration of the wiring parasitism ingredient of the printed circuit board
Masato Matsuo, Kazunori Hayami, Tatsuya Yamaguchi, Toshihiro Yamanaka (FUJITSU KYUSHU NETWORK TECHNOLOGIES), Muga Arai (FUJITSU ADVANCED TECHNOLOGIES) EE2014-17
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, a power supply circuit is a tendency of the low voltage and high current. This is for evolution of devices (FPGA etc.). In connection with this, the problem has occurred by voltage change when load current changes rapidly. For this reason, the power supply circuit's for telecom communication equipment using control IC which can control fast switching is expanding. As for the feedback loop characteristic of the power supply, 0 crossing frequency (frequency that Gain becomes 0db) shifts to the high frequency along with the fast switching. The power supply circuit is subject to the influence of parasitic capacitance & parasitic inductance of the printed-circuit board in order to control by high frequency. It is likely to become re-manufacturing the printed-circuit board, and it notices at the influence of parasitic capacitance & parasitic inductance. As for the power supply circuit, the simulation including parasitic capacitance & parasitic inductance of the printed-circuit board is indispensable to solve this.
Keyword (in Japanese) (See Japanese page) 
(in English) Power supply circuit simulation / Printed circuit board parasitic capacitance & parasitic inductance / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 240, EE2014-17, pp. 13-16, Oct. 2014.
Paper # EE2014-17 
Date of Issue 2014-10-03 (EE) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF EE2014-17

Conference Information
Committee EE  
Conference Date 2014-10-10 - 2014-10-10 
Place (in Japanese) (See Japanese page) 
Place (in English) The Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To EE 
Conference Code 2014-10-EE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) The power supply circuit simulation in consideration of the wiring parasitism ingredient of the printed circuit board 
Sub Title (in English)  
Keyword(1) Power supply circuit simulation  
Keyword(2) Printed circuit board parasitic capacitance & parasitic inductance  
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1st Author's Name Masato Matsuo  
1st Author's Affiliation FUJITSU KYUSHU NETWORK TECHNOLOGIES LIMITED (FUJITSU KYUSHU NETWORK TECHNOLOGIES)
2nd Author's Name Kazunori Hayami  
2nd Author's Affiliation FUJITSU KYUSHU NETWORK TECHNOLOGIES LIMITED (FUJITSU KYUSHU NETWORK TECHNOLOGIES)
3rd Author's Name Tatsuya Yamaguchi  
3rd Author's Affiliation FUJITSU KYUSHU NETWORK TECHNOLOGIES LIMITED (FUJITSU KYUSHU NETWORK TECHNOLOGIES)
4th Author's Name Toshihiro Yamanaka  
4th Author's Affiliation FUJITSU KYUSHU NETWORK TECHNOLOGIES LIMITED (FUJITSU KYUSHU NETWORK TECHNOLOGIES)
5th Author's Name Muga Arai  
5th Author's Affiliation FUJITSU ADVANCED TECHNOLOGIES LIMITED (FUJITSU ADVANCED TECHNOLOGIES)
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Speaker Author-1 
Date Time 2014-10-10 13:30:00 
Presentation Time 30 minutes 
Registration for EE 
Paper # EE2014-17 
Volume (vol) vol.114 
Number (no) no.240 
Page pp.13-16 
#Pages 4 
Date of Issue 2014-10-03 (EE) 

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