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Paper Abstract and Keywords
Presentation 2014-11-26 09:40
Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits
Kazushi Kawamura, Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-80 DC2014-34
Abstract (in Japanese) (See Japanese page) 
(in English) The propagation delay along each path inside an LSI widely varies depending on input data, and this property can be exploited to design high-performance approximation circuit with a negligible error rate.
In this paper, we propose a novel approximation circuit design algorithm, which identifies paths to be optimized based on input data and reconfigures these paths.
Our algorithm first identifies the optimized paths by incorporating timing error prediction circuits into a target circuit and running them in practice.
These paths are then dynamically reconfigured within an accuracy constraint with the objective of maximizing its performance.
Experimental results targeting a set of basic adders show that our algorithm can achieve performance increase by up to 18.5% within acceptable error of 2.1% compared with conventional design techniques.
Keyword (in Japanese) (See Japanese page) 
(in English) approximation circuit design / input data dependent / timing error prediction / reconfigurable device / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 328, VLD2014-80, pp. 51-56, Nov. 2014.
Paper # VLD2014-80 
Date of Issue 2014-11-19 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-80 DC2014-34

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To VLD 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Data Dependent Optimization using Suspicious Timing Error Prediction for Reconfigurable Approximation Circuits 
Sub Title (in English)  
Keyword(1) approximation circuit design  
Keyword(2) input data dependent  
Keyword(3) timing error prediction  
Keyword(4) reconfigurable device  
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1st Author's Name Kazushi Kawamura  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Shin-ya Abe  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Youhua Shi  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Masao Yanagisawa  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Nozomu Togawa  
5th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2014-11-26 09:40:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2014-80, DC2014-34 
Volume (vol) vol.114 
Number (no) no.328(VLD), no.329(DC) 
Page pp.51-56 
#Pages 6 
Date of Issue 2014-11-19 (VLD, DC) 

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