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Paper Abstract and Keywords
Presentation 2014-11-26 16:15
An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders
Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75
Abstract (in Japanese) (See Japanese page) 
(in English) In recent years, high speed and high precision computing is increasingly needed.
Hardware support for IEEE754 compliant quadruple precision arithmetic is expensive.
A computation time to perform double-double precision arithmetic which perform quadruple precision arithmetic by using two double precision floating point number
is 10 times larger than double precision arithmetic.
In this report, we propose a technique to enable high precision computing by
using multiple FP units and wide datapath for SIMD extensions.
We define an extended precision FP format which consist of a sign bit, 11-bit exponent, and 104-bit significand.
An extended FP number is stored in a 128-bit register.
An extended FP adder is designed by adding small hardware to two existing double precision FP adder,
and can calculate one extended precision ADD or two double-precision ADD.
We use a 128-bit datapath for SIMD extensions, then
we can easily treat a extended precision FP number without providing any new datapath.
Keyword (in Japanese) (See Japanese page) 
(in English) floating-point adder / extended-precision / double-precision / streaming SIMD extensions / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 330, CPSY2014-75, pp. 19-23, Nov. 2014.
Paper # CPSY2014-75 
Date of Issue 2014-11-19 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-75

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2014-11-26 - 2014-11-28 
Place (in Japanese) (See Japanese page) 
Place (in English) B-ConPlaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2014 -New Field of VLSI Design- 
Paper Information
Registration To CPSY 
Conference Code 2014-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders 
Sub Title (in English)  
Keyword(1) floating-point adder  
Keyword(2) extended-precision  
Keyword(3) double-precision  
Keyword(4) streaming SIMD extensions  
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1st Author's Name Hiroyuki Yataka  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Naofumi Takagi  
2nd Author's Affiliation Kyoto University (Kyoto Univ.)
3rd Author's Name Kazuyoshi Takagi  
3rd Author's Affiliation Kyoto University (Kyoto Univ.)
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Speaker Author-1 
Date Time 2014-11-26 16:15:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-75 
Volume (vol) vol.114 
Number (no) no.330 
Page pp.19-23 
#Pages 5 
Date of Issue 2014-11-19 (CPSY) 

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