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Paper Abstract and Keywords
Presentation 2014-12-01 15:15
[Poster Presentation] A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers
Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ) ICD2014-82 CPSY2014-94
Abstract (in Japanese) (See Japanese page) 
(in English) Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most microcontrollers achieve user-programmability by integrating non-volatile (NV) memories, such as flash memories for storing their programs. However, existing NV memories has a problem that the NV memory consumed large energy during memory access. This problem becomes even critical when lowering the power-supply voltage of NV microcontrollers to achieve power and energy reduction. In this paper, we try to solve this problem by introducing a transparent on-chip instruction cache which can reduce the NV memory access frequency. Unlike general-purpose microprocessors, it is important for microcontrollers used for real time applications in embedded systems that the program execution time can be calculated accurately prior to its execution. Our proposed instruction cache does not change the existing NV microcontroller's cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. Also we have conducted detailed microarchitecture design based on the architecture of a major industrial microcontroller, and we evaluated power and energy consumption for several benchmark programs. Evaluation result shows that the proposed instruction cache is effective for reducing power and energy consumption in a fairly wide range of practical NV microcontroller configurations.
Keyword (in Japanese) (See Japanese page) 
(in English) embedded-system / micro-controller / instruction cache / non-volatile / low power design / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 345, ICD2014-82, pp. 43-43, Dec. 2014.
Paper # ICD2014-82 
Date of Issue 2014-11-24 (ICD, CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2014-82 CPSY2014-94

Conference Information
Committee ICD CPSY  
Conference Date 2014-12-01 - 2014-12-02 
Place (in Japanese) (See Japanese page) 
Place (in English) Kikai-Shinko-Kaikan Bldg. 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To ICD 
Conference Code 2014-12-ICD-CPSY 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers 
Sub Title (in English)  
Keyword(1) embedded-system  
Keyword(2) micro-controller  
Keyword(3) instruction cache  
Keyword(4) non-volatile  
Keyword(5) low power design  
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1st Author's Name Dahoo Kim  
1st Author's Affiliation Hokkaido University (Hokkaido Univ)
2nd Author's Name Itaru Hida  
2nd Author's Affiliation Hokkaido University (Hokkaido Univ)
3rd Author's Name Tetsuya Asai  
3rd Author's Affiliation Hokkaido University (Hokkaido Univ)
4th Author's Name Masato Motomura  
4th Author's Affiliation Hokkaido University (Hokkaido Univ)
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Speaker Author-1 
Date Time 2014-12-01 15:15:00 
Presentation Time 120 minutes 
Registration for ICD 
Paper # ICD2014-82, CPSY2014-94 
Volume (vol) vol.114 
Number (no) no.345(ICD), no.346(CPSY) 
Page p.43 
#Pages 1 
Date of Issue 2014-11-24 (ICD, CPSY) 

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