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| Presentation | 2014-12-19 15:10 Studies on Reliability Evaluation Techniques for Triple Register Circuits Naoki Midorikawa, Muneyuki Nakamura, Aromhack Saysanasongkham, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)  DC2014-72 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper discusses the reliability evaluation technique for the triple register circuit which our research group had proposed. We firstly describe the summary of the triple register circuit. Secondary, the evaluation model by discrete time Markov chain is explained for calculating the numerical results within the practical time cost. Thus, we present the simulation on the basis of circuit information about the combinational circuit block in the target sequential one to estimate the transition probabilities of the Markov chain. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | transient fault / triple register circuit / reliability evaluation / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 384, DC2014-72, pp. 29-32, Dec. 2014. | |
| Paper # | DC2014-72 | |
| Date of Issue | 2014-12-12 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2014-72 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2014-12-19 - 2014-12-19 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Safety, etc. |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2014-12-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Studies on Reliability Evaluation Techniques for Triple Register Circuits |
| Sub Title (in English) | |
| Keyword(1) | transient fault |
| Keyword(2) | triple register circuit |
| Keyword(3) | reliability evaluation |
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| 1st Author's Name | Naoki Midorikawa |
| 1st Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 2nd Author's Name | Muneyuki Nakamura |
| 2nd Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 3rd Author's Name | Aromhack Saysanasongkham |
| 3rd Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 4th Author's Name | Kazuya Sakai |
| 4th Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
| 5th Author's Name | Satoshi Fukumoto |
| 5th Author's Affiliation | Tokyo Metropolitan University (Tokyo Metropolitan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2014-12-19 15:10:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2014-72 |
| Volume (vol) | vol.114 |
| Number (no) | no.384 |
| Page | pp.29-32 |
| #Pages | 4 |
| Date of Issue | 2014-12-12 (DC) |
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