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Paper Abstract and Keywords
Presentation 2015-01-29 17:40
Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits
Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ) VLD2014-129 CPSY2014-138 RECONF2014-62
Abstract (in Japanese) (See Japanese page) 
(in English) Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore, techniques for optimizing the supply and threshold voltages simultaneously under a specific delay constraint of LSI circuits are widely investigated over the past 15 years. However, only a few previous work investigate techniques for effectively reducing the energy consumption of circuits with a small number of different supply and threshold voltages. In this paper, we present several interesting properties which are very useful for reducing the energy consumption of circuits with a small number of different supply and threshold voltages. Those properties are numerically explained using analytical delay and energy consumption models. Through circuit simulation using a commercial 28nm process technology model, we demonstrate that the properties presented in this paper hold for actual LSI circuits.
Keyword (in Japanese) (See Japanese page) 
(in English) LSI Circuits / Low Energy Consumption / Supply Voltage / Threshold Voltage / Activity Factor / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 426, VLD2014-129, pp. 111-116, Jan. 2015.
Paper # VLD2014-129 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-129 CPSY2014-138 RECONF2014-62

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits 
Sub Title (in English)  
Keyword(1) LSI Circuits  
Keyword(2) Low Energy Consumption  
Keyword(3) Supply Voltage  
Keyword(4) Threshold Voltage  
Keyword(5) Activity Factor  
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1st Author's Name Toshihiro Takeshita  
1st Author's Affiliation Kyoto University (Kyoto Univ)
2nd Author's Name Shinichi Nishizawa  
2nd Author's Affiliation Kyoto University (Kyoto Univ)
3rd Author's Name AKM Mahfuzul Islam  
3rd Author's Affiliation Kyoto University (Kyoto Univ)
4th Author's Name Tohru Ishihara  
4th Author's Affiliation Kyoto University (Kyoto Univ)
5th Author's Name Hidetoshi Onodera  
5th Author's Affiliation Kyoto University (Kyoto Univ)
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Speaker Author-1 
Date Time 2015-01-29 17:40:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2014-129, CPSY2014-138, RECONF2014-62 
Volume (vol) vol.114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.111-116 
#Pages 6 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 

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