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Paper Abstract and Keywords
Presentation 2015-01-30 14:20
Reliability Management in 2-layered Supervisor Processor
Daiki Yamamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2014-144 CPSY2014-153 RECONF2014-77
Abstract (in Japanese) (See Japanese page) 
(in English) Computer systems are not only used in consumer electronics such as mobile phones and televisions but various industrial equipment such as a traffic control systems and medical devices.Space equipments and system which affecting human lives are required particularly high reliability.SVP (SuperVisor Processor) is a system for improving the reliability of the System.SVP guarantees the reliability of the system by the self-diagnosis and repair function.However, when the SVP fails, it cannot manage the system and becomes difficult to continuously operate the system.Therefore, we devide SVP function into 2-layered, Sys-SVP (System level SVP) and Hw-SVP (Hardware level SVP) to improve reliability.Sys-SVP is implemented in a part of processor core. and it manages and auxiliaries the entire system.Hw-SVP is implemented as a module with the highest reliability, and it tests, manages and recoveries the Sys-SVP.Hw-SVP is dependable due to its high reliability, and if failure occurs in Sys-SVP, Hw-SVP can recover it.In this way, SVP ensures high reliability to the system.In this paper, we consider the communication method to ensure reliability in the two-layered SVP.Then, we make a communication test between implemented Hw-SVP and pseudo Sys-SVP which is implemented on the PC.We confirm Hw-SVP working correctly from the test results.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Reliability / Supervisor Processor / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 427, CPSY2014-153, pp. 199-204, Jan. 2015.
Paper # CPSY2014-153 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-144 CPSY2014-153 RECONF2014-77

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To CPSY 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Reliability Management in 2-layered Supervisor Processor 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Reliability  
Keyword(3) Supervisor Processor  
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1st Author's Name Daiki Yamamoto  
1st Author's Affiliation Kumamoto University (Kumamoto Univ)
2nd Author's Name Morihiro Kuga  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ)
3rd Author's Name Motoki Amagasaki  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ)
4th Author's Name Masahiro Iida  
4th Author's Affiliation Kumamoto University (Kumamoto Univ)
5th Author's Name Toshinori Sueyoshi  
5th Author's Affiliation Kumamoto University (Kumamoto Univ)
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Speaker Author-1 
Date Time 2015-01-30 14:20:00 
Presentation Time 20 minutes 
Registration for CPSY 
Paper # VLD2014-144, CPSY2014-153, RECONF2014-77 
Volume (vol) vol.114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.199-204 
#Pages 6 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 

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