Information: Join today and make your research activities more affordable! Technical workshop participation fees and annual registration fees are available at member rates.
Notice: [Important] Announcement of Changes to Registration Fee Payment and Manuscript Upload Procedures for IEICE Technical Meetings
IEICE Technical Committee Submission System
Conference Paper's Information		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top Page Go Previous   [Japanese] / [English] 

Paper Abstract and Keywords
Presentation 2015-01-30 10:30
Error detection using residue signed-digit number arithmetic for arithmetic circuits
Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) VLD2014-136 CPSY2014-145 RECONF2014-69
Abstract (in Japanese) (See Japanese page) 
(in English) For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementation with compact and high speed performance.
In this paper, we propose an error detection circuit using a binary tree of an efficient residue Signed-Digit (SD) number adders, in which the residue SD addition is performed in the same constant time as an SD adder.
In detail, the circuits for converting the binary numbers to residue SD numbers and residue SD multiplication are designed in the structure of binary SD adder trees.
We merge the trees into efficient adder tree with the least addition stages.
We also discuss the relationship between the error bits and the moduli.
All two-bit errors of arithmetic can be detected by selecting two moduli.
The design experiments show that the proposed error detection circuits are high speed comparing to that using the binary arithmetic.
Keyword (in Japanese) (See Japanese page) 
(in English) Signed-Digit(SD) number / residue SD addition / residue SD multiplication / binary tree / Arithmetic error detection / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 426, VLD2014-136, pp. 151-156, Jan. 2015.
Paper # VLD2014-136 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2014-136 CPSY2014-145 RECONF2014-69

Conference Information
Committee RECONF CPSY VLD IPSJ-SLDM  
Conference Date 2015-01-29 - 2015-01-30 
Place (in Japanese) (See Japanese page) 
Place (in English) Hiyoshi Campus, Keio University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA Applications, etc 
Paper Information
Registration To VLD 
Conference Code 2015-01-RECONF-CPSY-VLD-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Error detection using residue signed-digit number arithmetic for arithmetic circuits 
Sub Title (in English)  
Keyword(1) Signed-Digit(SD) number  
Keyword(2) residue SD addition  
Keyword(3) residue SD multiplication  
Keyword(4) binary tree  
Keyword(5) Arithmetic error detection  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yoshitomo Nema  
1st Author's Affiliation Gunma University (Gunma Univ)
2nd Author's Name Yuuki Tanaka  
2nd Author's Affiliation Gunma University (Gunma Univ)
3rd Author's Name Kazuhiro Motegi  
3rd Author's Affiliation Gunma University (Gunma Univ)
4th Author's Name Shugang Wei  
4th Author's Affiliation Gunma University (Gunma Univ)
5th Author's Name  
5th Author's Affiliation ()
6th Author's Name  
6th Author's Affiliation ()
7th Author's Name  
7th Author's Affiliation ()
8th Author's Name  
8th Author's Affiliation ()
9th Author's Name  
9th Author's Affiliation ()
10th Author's Name  
10th Author's Affiliation ()
11th Author's Name  
11th Author's Affiliation ()
12th Author's Name  
12th Author's Affiliation ()
13th Author's Name  
13th Author's Affiliation ()
14th Author's Name  
14th Author's Affiliation ()
15th Author's Name  
15th Author's Affiliation ()
16th Author's Name  
16th Author's Affiliation ()
17th Author's Name  
17th Author's Affiliation ()
18th Author's Name  
18th Author's Affiliation ()
19th Author's Name  
19th Author's Affiliation ()
20th Author's Name  
20th Author's Affiliation ()
21st Author's Name  
21st Author's Affiliation ()
22nd Author's Name  
22nd Author's Affiliation ()
23rd Author's Name  
23rd Author's Affiliation ()
24th Author's Name  
24th Author's Affiliation ()
25th Author's Name  
25th Author's Affiliation ()
26th Author's Name / /
26th Author's Affiliation ()
()
27th Author's Name / /
27th Author's Affiliation ()
()
28th Author's Name / /
28th Author's Affiliation ()
()
29th Author's Name / /
29th Author's Affiliation ()
()
30th Author's Name / /
30th Author's Affiliation ()
()
31st Author's Name / /
31st Author's Affiliation ()
()
32nd Author's Name / /
32nd Author's Affiliation ()
()
33rd Author's Name / /
33rd Author's Affiliation ()
()
34th Author's Name / /
34th Author's Affiliation ()
()
35th Author's Name / /
35th Author's Affiliation ()
()
36th Author's Name / /
36th Author's Affiliation ()
()
Speaker Author-1 
Date Time 2015-01-30 10:30:00 
Presentation Time 20 minutes 
Registration for VLD 
Paper # VLD2014-136, CPSY2014-145, RECONF2014-69 
Volume (vol) vol.114 
Number (no) no.426(VLD), no.427(CPSY), no.428(RECONF) 
Page pp.151-156 
#Pages 6 
Date of Issue 2015-01-22 (VLD, CPSY, RECONF) 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan