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| Presentation | 2015-02-13 14:55 A Method of Scheduling in High-Level Synthesis for Hierarchical Testability Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.)  DC2014-84 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We previously proposed a binding method for hierarchical testability to increase the number of hierarchically testable functional units in hierarchical testing using control data flow graphs. This paper proposes a scheduling method for hierarchical testability to increase the efficiency of the binding method for hierarchical testability. Our proposed method is based on two kinds of scheduling strategies using results of test environment generation. Experimental results show that the combination of our proposed scheduling method with the binding method for hierarchical testability can increase the number of hierarchically testable functional units, and can achieve high fault coverage in hierarchical testing. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | high-level synthesis / scheduling / binding / hierarchical testing / test environments / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 446, DC2014-84, pp. 37-42, Feb. 2015. | |
| Paper # | DC2014-84 | |
| Date of Issue | 2015-02-06 (DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | DC2014-84 |
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| Conference Information | |
| Committee | DC |
| Conference Date | 2015-02-13 - 2015-02-13 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kikai-Shinko-Kaikan Bldg |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | VLSI Design and Test, etc |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2015-02-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Method of Scheduling in High-Level Synthesis for Hierarchical Testability |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis |
| Keyword(2) | scheduling |
| Keyword(3) | binding |
| Keyword(4) | hierarchical testing |
| Keyword(5) | test environments |
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| 1st Author's Name | Jun Nishimaki |
| 1st Author's Affiliation | Nihon University (Nihon Univ.) |
| 2nd Author's Name | Toshinori Hosokawa |
| 2nd Author's Affiliation | Nihon University (Nihon Univ.) |
| 3rd Author's Name | Hideo Fujiwara |
| 3rd Author's Affiliation | Osaka Gakuin University (Osaka Gakuin Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-02-13 14:55:00 |
| Presentation Time | 25 minutes |
| Registration for | DC |
| Paper # | DC2014-84 |
| Volume (vol) | vol.114 |
| Number (no) | no.446 |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2015-02-06 (DC) |
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