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Paper Abstract and Keywords
Presentation 2015-03-06 15:15
Adaptive Error Correcting Code by Priority on RMT Processor
Tsukasa Matsui, Shuma Hagiwara, Keigo Mizotani, Nobuyuki Yamasaki (Keio Univ.) CPSY2014-167 DC2014-93
Abstract (in Japanese) (See Japanese page) 
(in English) In embedded real-time systems such as robots, there are requirements for real-time constraints, high throughput and low energy consumption. Responsive Multithreaded Processor (RMT Processor), 8-way prioritized simultaneous multithreaded processor, makes use of the characteristics of SMT and controls threads with priorities. Therefore, RMT Processor achives these requirements. In recent years, reliability has also been required in embedded systems because of soft errors by radiation. Generaly, high priority thread tend to require much reliability. Considering trade-off between reliability and low energy consumption on low priority threads, we design a method to dynamically switch error correcting codes. By degrading intensity level of error correcting codes duaring the execution of threads with lower priorities, the number of switchings per parity decreases, which prevents increases of energy consumption.
Keyword (in Japanese) (See Japanese page) 
(in English) RMT Processor / ECC / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 506, CPSY2014-167, pp. 31-36, March 2015.
Paper # CPSY2014-167 
Date of Issue 2015-02-27 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee CPSY IPSJ-EMB IPSJ-SLDM DC  
Conference Date 2015-03-06 - 2015-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2015-03-CPSY-EMB-SLDM-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Adaptive Error Correcting Code by Priority on RMT Processor 
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Keyword(1) RMT Processor  
Keyword(2) ECC  
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1st Author's Name Tsukasa Matsui  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Shuma Hagiwara  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Keigo Mizotani  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Nobuyuki Yamasaki  
4th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2015-03-06 15:15:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-167, DC2014-93 
Volume (vol) vol.114 
Number (no) no.506(CPSY), no.507(DC) 
Page pp.31-36 
#Pages 6 
Date of Issue 2015-02-27 (CPSY, DC) 

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