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Paper Abstract and Keywords
Presentation 2015-03-06 14:50
A Resource Utilization Aware Method to Improve Throughput on RMT Processor
Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, Nobuyuki Yamasaki (Keio Univ.) CPSY2014-166 DC2014-92
Abstract (in Japanese) (See Japanese page) 
(in English) SMT (Simultaneous MultiThreading) architecture is suitable for embedded processors which have area
constraints, it is because SMT can improve functional unit utilization via sharing resources between threads. On the
other hand, SMT degrades execution time predictability because of resource conflicts. To deal with this problem,
RMTP (Responsive MultiThread Processor) has an IPC (Instruction Per Clock cycle) control mechanism to improve
execution time predictability. In this paper, we classify threads to real-time thread and non-real-time thread, and
propose a method to improve throughput of non-real-time threads while minimizing performance degradation on
real-time threads. We set both real-time threads and non-real-time threads to two and do RTL simulation. As a
result, our method improves average IPC of non-real-time threads by 10 % not degrading real-time threads.
Keyword (in Japanese) (See Japanese page) 
(in English) Embedded Processor / Simultaneous MultiThreading / Real-Time Processing / IPC Control / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 506, CPSY2014-166, pp. 25-30, March 2015.
Paper # CPSY2014-166 
Date of Issue 2015-02-27 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-166 DC2014-92

Conference Information
Committee CPSY IPSJ-EMB IPSJ-SLDM DC  
Conference Date 2015-03-06 - 2015-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To CPSY 
Conference Code 2015-03-CPSY-EMB-SLDM-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Resource Utilization Aware Method to Improve Throughput on RMT Processor 
Sub Title (in English)  
Keyword(1) Embedded Processor  
Keyword(2) Simultaneous MultiThreading  
Keyword(3) Real-Time Processing  
Keyword(4) IPC Control  
Keyword(5)  
Keyword(6)  
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Keyword(8)  
1st Author's Name Taro Murata  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Kensuke Kaneda  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Masayoshi Takasu  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Keigo Mizotani  
4th Author's Affiliation Keio University (Keio Univ.)
5th Author's Name Yusuke Hatori  
5th Author's Affiliation Keio University (Keio Univ.)
6th Author's Name Nobuyuki Yamasaki  
6th Author's Affiliation Keio University (Keio Univ.)
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Speaker Author-1 
Date Time 2015-03-06 14:50:00 
Presentation Time 25 minutes 
Registration for CPSY 
Paper # CPSY2014-166, DC2014-92 
Volume (vol) vol.114 
Number (no) no.506(CPSY), no.507(DC) 
Page pp.25-30 
#Pages 6 
Date of Issue 2015-02-27 (CPSY, DC) 

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