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Paper Abstract and Keywords
Presentation 2015-03-07 13:00
Study of Cost Reduction Technique for FPGA-based Control Systems by Quantitative Evaluation of Dangerous Failure Ratio
Teppei Hirotsu, Tadanobu Toba (Hitachi) CPSY2014-180 DC2014-106
Abstract (in Japanese) (See Japanese page) 
(in English) FPGA is one of promising device to gain the performance of embedded systems with the progress of speed-up and cost reduction of FPGA. However, soft error rate of FPGS is larger than that of ASIC, redundant architecture is used to mitigate the soft error. For reduce the cost overhead of redundant architecture, we propose the optimized dependable architecture based on the quantitative evaluation of dangerous failure ratio. Model checking method is used for the evaluation and we show the preliminary results of the evaluation method in this paper.
Keyword (in Japanese) (See Japanese page) 
(in English) FPGA / Dependable system / Model checking / / / / /  
Reference Info. IEICE Tech. Rep., vol. 114, no. 507, DC2014-106, pp. 119-124, March 2015.
Paper # DC2014-106 
Date of Issue 2015-02-27 (CPSY, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2014-180 DC2014-106

Conference Information
Committee CPSY IPSJ-EMB IPSJ-SLDM DC  
Conference Date 2015-03-06 - 2015-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To DC 
Conference Code 2015-03-CPSY-EMB-SLDM-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Study of Cost Reduction Technique for FPGA-based Control Systems by Quantitative Evaluation of Dangerous Failure Ratio 
Sub Title (in English)  
Keyword(1) FPGA  
Keyword(2) Dependable system  
Keyword(3) Model checking  
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1st Author's Name Teppei Hirotsu  
1st Author's Affiliation Hitachi Ltd. (Hitachi)
2nd Author's Name Tadanobu Toba  
2nd Author's Affiliation Hitachi Ltd. (Hitachi)
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Speaker Author-1 
Date Time 2015-03-07 13:00:00 
Presentation Time 25 minutes 
Registration for DC 
Paper # CPSY2014-180, DC2014-106 
Volume (vol) vol.114 
Number (no) no.506(CPSY), no.507(DC) 
Page pp.119-124 
#Pages 6 
Date of Issue 2015-02-27 (CPSY, DC) 

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