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| Presentation | 2015-03-07 10:20 Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami (Waseda Univ.), Uichiro Takahashi, Sakae Inoue (Fujitsu), Keiji Kimura, Hironori Kasahara (Waseda Univ.)  CPSY2014-178 DC2014-104 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a dynamic scheduling algorithm for multiple automatically parallelized or power reduced applications on a multicore smart devices to gain higher performance and lower power comsumption within the application's deadline. This scheduling algorithm uses the information such as time, power, deadline and number of cores for each application, and is composed of three type of scheduling. Using media codec applications as a benchmark, the proposed scheduling gained 18.5% speedup and 28.8% power reduction compared to FIFO scheduling. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Scheduling / Parallelized Application / Multicore / ARM / Power Reduction / Acceleration / / | |
| Reference Info. | IEICE Tech. Rep., vol. 114, no. 506, CPSY2014-178, pp. 95-100, March 2015. | |
| Paper # | CPSY2014-178 | |
| Date of Issue | 2015-02-27 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2014-178 DC2014-104 |
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| Conference Information | |
| Committee | CPSY IPSJ-EMB IPSJ-SLDM DC |
| Conference Date | 2015-03-06 - 2015-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | CPSY |
| Conference Code | 2015-03-CPSY-EMB-SLDM-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems |
| Sub Title (in English) | |
| Keyword(1) | Scheduling |
| Keyword(2) | Parallelized Application |
| Keyword(3) | Multicore |
| Keyword(4) | ARM |
| Keyword(5) | Power Reduction |
| Keyword(6) | Acceleration |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Takashi Goto |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Kohei Muto |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Tomohiro Hirano |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Hiroki Mikami |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Uichiro Takahashi |
| 5th Author's Affiliation | Fujitsu Limited (Fujitsu) |
| 6th Author's Name | Sakae Inoue |
| 6th Author's Affiliation | Fujitsu Limited (Fujitsu) |
| 7th Author's Name | Keiji Kimura |
| 7th Author's Affiliation | Waseda University (Waseda Univ.) |
| 8th Author's Name | Hironori Kasahara |
| 8th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-03-07 10:20:00 |
| Presentation Time | 25 minutes |
| Registration for | CPSY |
| Paper # | CPSY2014-178, DC2014-104 |
| Volume (vol) | vol.114 |
| Number (no) | no.506(CPSY), no.507(DC) |
| Page | pp.95-100 |
| #Pages | 6 |
| Date of Issue | 2015-02-27 (CPSY, DC) |
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