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Paper Abstract and Keywords
Presentation 2015-06-20 14:00
On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors
Hanpei Koike, Masakazu Hioki, Yasuhiro Ogasahara (AIST), Hayato Ishigaki, Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST) RECONF2015-22
Abstract (in Japanese) (See Japanese page) 
(in English) Flex Power FPGA utilizes threshold voltage programmability to reduce its static power by the body bias control of circuit blocks in the FPGA. We have been developing a series of Flex Power FPGA chips using SOTB (Silicon On Thin BOX) transistor so far. The last 4th chip is functionally enhanced, in order to embed it on the evaluation board, and to enable practical use and evaluation by mapping more practical application circuits, pulling out of basic data measuring as a experimental chip. A new evaluation board called AISTino, which is equipped with the new chip, has been also developed. In this paper, we are going to describe the overview of them.
Keyword (in Japanese) (See Japanese page) 
(in English) SOTB / FPGA / Body Bias Control / Static Power Reduction / Low Voltage Operation / Minimum Energy Operation / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 109, RECONF2015-22, pp. 119-124, June 2015.
Paper # RECONF2015-22 
Date of Issue 2015-06-12 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Notes on Review This article is a technical report without peer review, and its polished version will be published elsewhere.
Download PDF RECONF2015-22

Conference Information
Committee RECONF  
Conference Date 2015-06-19 - 2015-06-20 
Place (in Japanese) (See Japanese page) 
Place (in English) Kyoto University 
Topics (in Japanese) (See Japanese page) 
Topics (in English) the 10th anniversary celebration of RECONF: Reconfigurable Systems, etc. 
Paper Information
Registration To RECONF 
Conference Code 2015-06-RECONF 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors 
Sub Title (in English)  
Keyword(1) SOTB  
Keyword(2) FPGA  
Keyword(3) Body Bias Control  
Keyword(4) Static Power Reduction  
Keyword(5) Low Voltage Operation  
Keyword(6) Minimum Energy Operation  
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Keyword(8)  
1st Author's Name Hanpei Koike  
1st Author's Affiliation National Instituteof Advanced Industrial Science and Technology (AIST)
2nd Author's Name Masakazu Hioki  
2nd Author's Affiliation National Instituteof Advanced Industrial Science and Technology (AIST)
3rd Author's Name Yasuhiro Ogasahara  
3rd Author's Affiliation National Instituteof Advanced Industrial Science and Technology (AIST)
4th Author's Name Hayato Ishigaki  
4th Author's Affiliation Meiji University (Meiji Univ.)
5th Author's Name Toshiyuki Tsutsumi  
5th Author's Affiliation Meiji University (Meiji Univ.)
6th Author's Name Tadashi Nakagawa  
6th Author's Affiliation National Instituteof Advanced Industrial Science and Technology (AIST)
7th Author's Name Toshihiro Sekigawa  
7th Author's Affiliation National Instituteof Advanced Industrial Science and Technology (AIST)
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Speaker Author-1 
Date Time 2015-06-20 14:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2015-22 
Volume (vol) vol.115 
Number (no) no.109 
Page pp.119-124 
#Pages
Date of Issue 2015-06-12 (RECONF) 


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