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Paper Abstract and Keywords
Presentation 2015-08-04 14:30
A Feasibility Study on Implementing Micro-ITRON Task Scheduler by Wired-logic
Kouichi Araki (Godai Kaihatsu), Tomoaki Ukezono (Fukuoka Univ.) CPSY2015-20
Abstract (in Japanese) (See Japanese page) 
(in English) Software overheads which are caused by task scheduler inside operating systems have possibility of fluctuation. It impairs accuracy in approximation of completion time for individual task, and it might make real-time performance worse on embedded systems. On the other hand, until now, integration degree of transistor has continued to increase by build-out of recent fine processing technology. Consequently, this paper considers how scale of task scheduler can be achieved using wired-logic by the recent fine processing technology as an example for micro-ITRON task schedulers.
Keyword (in Japanese) (See Japanese page) 
(in English) Task Scheduler / Wired-logic / Micro-ITRON / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 174, CPSY2015-20, pp. 53-58, Aug. 2015.
Paper # CPSY2015-20 
Date of Issue 2015-07-28 (CPSY) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPSY2015-20

Conference Information
Committee CPSY DC IPSJ-ARC  
Conference Date 2015-08-04 - 2015-08-06 
Place (in Japanese) (See Japanese page) 
Place (in English) B-Con Plaza (Beppu) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Parallel, Distributed and Cooperative Processing 
Paper Information
Registration To CPSY 
Conference Code 2015-08-CPSY-DC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Feasibility Study on Implementing Micro-ITRON Task Scheduler by Wired-logic 
Sub Title (in English)  
Keyword(1) Task Scheduler  
Keyword(2) Wired-logic  
Keyword(3) Micro-ITRON  
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1st Author's Name Kouichi Araki  
1st Author's Affiliation Godai Kaihatsu Corporation (Godai Kaihatsu)
2nd Author's Name Tomoaki Ukezono  
2nd Author's Affiliation Fukuoka University (Fukuoka Univ.)
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Speaker Author-1 
Date Time 2015-08-04 14:30:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # CPSY2015-20 
Volume (vol) vol.115 
Number (no) no.174 
Page pp.53-58 
#Pages 6 
Date of Issue 2015-07-28 (CPSY) 

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