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Paper Abstract and Keywords
Presentation 2015-09-03 15:00
Performance Evaluation of 802.11a Viterbi Decoder for IoT Applications
Hiromasa Kato, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) SIS2015-22
Abstract (in Japanese) (See Japanese page) 
(in English) This research is our first step on the purpose of developing low-complex Viterbi decoder for IoT applications. We evaluate how the values of Viterbi decoder’s parameters such as trace back length (L), input data bit-width (D), and LLR truncated value (E), affects to BER and PER of a communication system. The IEEE 802.11a simulator is used because it is considered to be suitable for IoT applications. Our simulation results show that both BER and PER performance are improved if L value increased. However, if L is large enough, i.e., L ≥ 60, the performance improvement becomes insignificant. In addition, both BER and PER performance are continuously improved if D value increases from 1 to 5 bits. The best improvement of both BER performance (i.e., 1.8dB) and PER performance (i.e., 1.5dB) can be seen when D increases from 2 to 3 bits. Thus D = 3 is proposed for Viterbi decoder’s hardware development. Surprisingly, when D > 5 both BER and PER performance are degraded if D increases. Finally, our research shows that truncating the LLR value to E = 1.75 helps the Viterbi decoder achieves the best BER and PER performance in case D = 3 bits. Base on these research results, we come to the conclude of using 20 ≤ L ≤ 40, D = 3 bits, and E ≈ 1.75 for future development of low complex Viterbi decoder circuit for IoT applications. Furthermore, in this paper we introduce some mathematics equations for simplifying the Viterbi decoder process.
Keyword (in Japanese) (See Japanese page) 
(in English) Wireless Network / IoT / Wi-Fi / / / / /  
Reference Info. IEICE Tech. Rep., vol. 115, no. 208, SIS2015-22, pp. 43-49, Sept. 2015.
Paper # SIS2015-22 
Date of Issue 2015-08-27 (SIS) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF SIS2015-22

Conference Information
Committee SIS IPSJ-AVM  
Conference Date 2015-09-03 - 2015-09-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kansai Univ. 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Smart Multimedia Systems, etc. 
Paper Information
Registration To SIS 
Conference Code 2015-09-SIS-AVM 
Language English (Japanese title is available) 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance Evaluation of 802.11a Viterbi Decoder for IoT Applications 
Sub Title (in English)  
Keyword(1) Wireless Network  
Keyword(2) IoT  
Keyword(3) Wi-Fi  
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1st Author's Name Hiromasa Kato  
1st Author's Affiliation Nara Institute of Science and Technology (NAIST)
2nd Author's Name Tran Thi Hong  
2nd Author's Affiliation Nara Institute of Science and Technology (NAIST)
3rd Author's Name Shinya Takamaeda  
3rd Author's Affiliation Nara Institute of Science and Technology (NAIST)
4th Author's Name Yasuhiko Nakashima  
4th Author's Affiliation Nara Institute of Science and Technology (NAIST)
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Speaker Author-1 
Date Time 2015-09-03 15:00:00 
Presentation Time 20 minutes 
Registration for SIS 
Paper # SIS2015-22 
Volume (vol) vol.115 
Number (no) no.208 
Page pp.43-49 
#Pages 7 
Date of Issue 2015-08-27 (SIS) 

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