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| Presentation | 2015-12-02 17:35 A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)  VLD2015-54 DC2015-50 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a circuit and then may degrade operation frequency. We must consider interconnection delays and clock skews in floorplan-aware FPGA-HLS flow to design circuits having small latency. In this paper, we propose a floorplan-aware high-level synthesis algorithm for FPGA designs optimizing operation frequency of a circuit by improving interconnection delays and clock skews on the critical-path. Our target architecture is HDR, one of distributed-register architectures, and then we can consider module floorplan easily. Based on it, we estimate the delay of each signal path including interconnection delays and clock-skews, and identify the critical-path. To optimize them, we propose a novel scheduling/FU binding method and a novel floorplanning method. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the latency by up to 24% compared with conventional approaches. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | high-level synthesis (HLS) / FPGA / clock skew / interconnection delay / floorplan / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 115, no. 338, VLD2015-54, pp. 99-104, Dec. 2015. | |
| Paper # | VLD2015-54 | |
| Date of Issue | 2015-11-24 (VLD, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2015-54 DC2015-50 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2015-12-01 - 2015-12-03 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nagasaki Kinro Fukushi Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2015 -New Field of VLSI Design- |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2015-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis (HLS) |
| Keyword(2) | FPGA |
| Keyword(3) | clock skew |
| Keyword(4) | interconnection delay |
| Keyword(5) | floorplan |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Koichi Fujiwara |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | kazushi Kawamura |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Masao Yanagisawa |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Nozomu Togawa |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2015-12-02 17:35:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2015-54, DC2015-50 |
| Volume (vol) | vol.115 |
| Number (no) | no.338(VLD), no.339(DC) |
| Page | pp.99-104 |
| #Pages | 6 |
| Date of Issue | 2015-11-24 (VLD, DC) |
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